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MULTIPLEXING LATCH CIRCUIT AND METHOD. February 21, 2019: US20190058476-A1

A circuit includes a clock generator configured to generate a first latching clock signal and a second latching clock signal. Responsive to a select signal, one of the first latching clock signal or the second latching clock signal has a clock signal frequency and the other of the first latching clo ...


62
ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION. April 11, 2019: US20190109129-A1

Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first c ...