1
Takashi Kato, Masao Taguchi: Three-dimensional integrated circuit and manufacturing method thereof. Fujitsu, Staas & Halsey, July 3, 1990: US04939568 (316 worldwide citation)

The present invention is directed to a three-dimensional stacked IC and a method for forming a three-dimensional stacked IC on a base plate. The three-dimensional stacked IC includes a unit semiconductor IC, which has constituent ICs formed on either one surface or on both surfaces of a substrate. I ...


2
John K Woodman: Three dimensional integrated circuit package. Flehr Hohbach Test Albritton & Herbert, May 14, 1991: US05016138 (279 worldwide citation)

This invention discloses a three-dimensional, high density package for integrated circuits for which integrated circuits are placed onto substrate layers and then stacked together. Techniques for interconnecting the layers to one another and for connecting the layers to external circuitry are also d ...


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Peter Ramm, Reinhold Buchner: Method of making a three-dimensional integrated circuit. Fraunhofer Gesellschaft zur F orderung der angewandten Forschung e V, Karl Hormann, October 8, 1996: US05563084 (256 worldwide citation)

A method of making a three dimensionally integrated circuit by connecting first and second substrates (1;7) provided with devices in at least one layer in at least one surface in each of said substrates. An auxiliary substrate is connected to the one surface of one of said substrates which is then r ...


5
Sang Yun Lee: Method for making a three-dimensional integrated circuit structure. Werner & Axenfeld PC, May 30, 2006: US07052941 (248 worldwide citation)

Vertically oriented semiconductor devices may be added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor devices are physically separated from each other, and are not disposed within the same semiconductor bo ...


6
Ronald M Finnila: Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate. Hughes Aircraft Company, W C Schubert, W K Denson Low, June 20, 1995: US05426072 (233 worldwide citation)

A method of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI wafer includes a silicon layer separated from a bulk silicon substrate by a layer of dielectric material, typically SiO2. Next, at least one electrical feedthrough is formed in each of the silicon layers an ...


7
Chen Chung Hsu: Trench method for three dimensional chip connecting during IC fabrication. United Microelectronics Corporation, William H Wright, May 6, 1997: US05627106 (207 worldwide citation)

A new method of connecting three-dimensional integrated circuit chips using trench technology is described. Semiconductor device structures are provided in and on the top side of a semiconductor substrate of a first and a second three-dimensional integrated circuit chip. Deep trenches are etched int ...


8
John K Woodman: Three dimensional integrated circuit package. Flehr Hohbach Test Albritton & Herbert, September 19, 1989: US04868712 (206 worldwide citation)

This invention discloses a three-dimensional, high density package for integrated circuits for which integrated circuits are placed onto substrate layers and then stacked together. Techniques for interconnecting the layers to one another and for connecting the layers to external circuitry are also d ...


9
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Charles W Koburger III: Accessible chip stack and process of manufacturing thereof. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph Petrokaitis Esq, May 5, 2009: US07528494 (160 worldwide citation)

A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip de ...


10
David Staines, Grant M Kloster, Shriram Ramanathan: Method to fill the gap between coupled wafers. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 8, 2006: US07087538 (146 worldwide citation)

A three-dimensional integrated circuit formed by applying a material to fill a gap between coupled wafers and slicing the coupled wafers into dice. A method for filling a gap between coupled wafers. Various embodiments include at least one of spinning a coupled wafer pair, drilling a hole into one o ...



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