41
Jonathan D Bradbury, Michael K Gschwind, Christian Jacobi, Eric M Schwarz, Timothy J Slegel: Instruction to compute the distance to a specified memory boundary. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman, Matthew M Hulihan, Heslin Rothenberg Farley & Mesiti PC, July 18, 2017: US09710267

A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, ...


42
Michael K Gschwind, Valentina Salapura: Partition mobility for partitions with extended code. INTERNATIONAL BUSINESS MACHINES CORPORATION, Steven L Bennett, Matthew M Hulihan, Heslin Rothenberg Farley & Mesiti P C, January 2, 2018: US09858058

A partition mobility facility in which a partition that is executing one or more applications that have optimized code with one or more extended features is to be moved from a source system to a target system. If the target system does not support the extended mode features, then action is taken to ...


43
Michael K Gschwind, Valentina Salapura: Partition mobility for partitions with extended code. INTERNATIONAL BUSINESS MACHINES CORPORATION, Steven L Bennett, Matthew M Hulihan, Heslin Rothenberg Farley & Mesiti PC, January 16, 2018: US09870210

A partition mobility facility in which a partition that is executing one or more applications that have optimized code with one or more extended features is to be moved from a source system to a target system. If the target system does not support the extended mode features, then action is taken to ...


44
Michael K Gschwind, Valentina Salapura: Predictive fetching and decoding for selected instructions. INTERNATIONAL BUSINESS MACHINES CORPORATION, Steven Chiu Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, March 20, 2018: US09921843

Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instructi ...


45
Dan F Greiner, Bernd Nerz, Tamas Visegrady: Instruction for performing a pseudorandom number seed operation. INTERNATIONAL BUSINESS MACHINES CORPORATION, Steven Chiu Esq, Kevin P Radigan Esq, Heslin Rothenberg Farley & Mesiti, January 2, 2018: US09860056

A machine instruction is provided that has associated therewith an opcode to identify a perform pseudorandom number operation, and an operand to be used by the machine instruction. The machine instruction is executed, and execution includes obtaining a modifier indicator. Based on the modifier indic ...


46
Michael K Gschwind, Valentina Salapura: Hierarchical translation structures providing separate translations for instruction fetches and data accesses. International Business Machines Corporation, Heslin Rothenberg Farley & Mesiti P C, July 25, 2017: US09715449

Hierarchical address translation structures providing separate translations for instruction fetches and data accesses. An address is to be translated from the address to another address using a hierarchy of address translation structures. The hierarchy of address translation structures includes a pl ...


47
Michael K Gschwind, Valentina Salapura: Hierarchical translation structures providing separate translations for instruction fetches and data accesses. International Business Machines Corporation, Heslin Rothenberg Farley & Mesiti P C, July 18, 2017: US09710382

Hierarchical address translation structures providing separate translations for instruction fetches and data accesses. An address is to be translated from the address to another address using a hierarchy of address translation structures. The hierarchy of address translation structures includes a pl ...


48
Anthony J Bybell, Michael K Gschwind: Separate memory address translations for instruction fetches and data accesses. International Business Machines Corporation, Heslin Rothenberg Farley & Mesiti P C, August 15, 2017: US09734083

An address translation capability in which a processor obtains an address to be translated, and translates the address from the address to the another address. The translating includes determining an attribute of the address to be translated, and based on the attribute being a first attribute, first ...


49
Anthony J Bybell, Michael K Gschwind: Separate memory address translations for instruction fetches and data accesses. International Business Machines Corporation, Heslin Rothenberg Farley & Mesiti P C, August 15, 2017: US09734084

An address translation capability in which a processor obtains an address to be translated, and translates the address from the address to the another address. The translating includes determining an attribute of the address to be translated, and based on the attribute being a first attribute, first ...


50
Michael K Gschwind: Address translation structures to provide separate translations for instruction fetches and data accesses. International Business Machines Corporation, Heslin Rothenberg Farley & Mesiti P C, November 21, 2017: US09824022

An address translation capability in which information is obtained from an address translation structure to be used to translate a first address to a second address, the first address being of a first address type and the second address being of a second address type. The address translation structu ...