1
Frank J Gorishek IV, Charles R Boswell Jr, David W Smith: Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system. Advanced Micro Devices, Lawrence J Merkel, Conley Rose & Tayon PC, October 23, 2001: US06308255 (320 worldwide citation)

A computer system includes a host processor and an emulation coprocessor. The host processor includes hardware configured to execute instructions defined by a host instruction set architecture, while the emulation coprocessor includes hardware configured to execute instructions defined by a differen ...


2
Michael K Gschwind: Forming instruction groups based on decode time instruction optimization. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, June 13, 2017: US09678756 (3 worldwide citation)

Instructions are grouped into instruction groups based on optimizations that may be performed. An instruction is obtained, and a determination is made as to whether the instruction is to be included in a current instruction group or another instruction group. This determination is made based on whet ...


3
Michael K Gschwind: Forming instruction groups based on decode time instruction optimization. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, June 13, 2017: US09678757 (3 worldwide citation)

Instructions are grouped into instruction groups based on optimizations that may be performed. An instruction is obtained, and a determination is made as to whether the instruction is to be included in a current instruction group or another instruction group. This determination is made based on whet ...


4
Michael K Gschwind, Valentina Salapura: Predictive fetching and decoding for selected instructions. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, April 11, 2017: US09619230 (1 worldwide citation)

Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instructi ...


5
Michael K Gschwind, Valentina Salapura: Predictive fetching and decoding for selected instructions. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, April 11, 2017: US09619232 (1 worldwide citation)

Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instructi ...


6
Michael K Gschwind, Valentina Salapura: Predictor data structure for use in pipelined processing. GLOBALFOUNDRIES, Heslin Rothenberg Farley & Mesiti P C, Nathan Davis, Nicholas Mesiti, January 3, 2017: US09535703 (1 worldwide citation)

A predictor data structure is used for pipelined processing by a pipelined processor. The predictor data structure includes a predicted address to be used in return from execution of a selected instruction, and a predicted operating state associated with the predicted address. Based on determining a ...


7
Dan F Greiner, Christian Jacobi, Timothy J Slegel: Restricted instructions in transactional execution. INTERNATIONAL BUSINESS MACHINES CORPORATION, Steven Chiu Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, December 26, 2017: US09851978

Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are ...


8
Dan F Greiner, Christian Jacobi, Timothy J Slegel: Restricted instructions in transactional execution. INTERNATIONAL BUSINESS MACHINES CORPORATION, Steven Chiu Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, January 2, 2018: US09858082

Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are ...


9
Dan F Greiner, Christian Jacobi, Timothy J Slegel: Transaction abort processing. INTERNATIONAL BUSINESS MACHINES CORPORATION, Steven Chiu Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, November 7, 2017: US09811337

A transaction executing within a computing environment ends prior to completion; i.e., execution is aborted. Pursuant to aborting execution, a hardware transactional execution CPU mode is exited, and one or more of the following is performed: restoring selected registers; committing nontransactional ...


10
Dan F Greiner, Christian Jacobi, Timothy J Slegel: Saving/restoring selected registers in transactional processing. INTERNATIONAL BUSINESS MACHINES CORPORATION, Steven Chiu Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, October 17, 2017: US09792125

A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not acces ...



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