1
Frank J Gorishek IV, Charles R Boswell Jr, David W Smith: Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system. Advanced Micro Devices, Lawrence J Merkel, Conley Rose & Tayon PC, October 23, 2001: US06308255 (295 worldwide citation)

A computer system includes a host processor and an emulation coprocessor. The host processor includes hardware configured to execute instructions defined by a host instruction set architecture, while the emulation coprocessor includes hardware configured to execute instructions defined by a differen ...


2
Michael K Gschwind: Forming instruction groups based on decode time instruction optimization. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, June 13, 2017: US09678757 (2 worldwide citation)

Instructions are grouped into instruction groups based on optimizations that may be performed. An instruction is obtained, and a determination is made as to whether the instruction is to be included in a current instruction group or another instruction group. This determination is made based on whet ...


3
Michael K Gschwind: Forming instruction groups based on decode time instruction optimization. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, June 13, 2017: US09678756 (2 worldwide citation)

Instructions are grouped into instruction groups based on optimizations that may be performed. An instruction is obtained, and a determination is made as to whether the instruction is to be included in a current instruction group or another instruction group. This determination is made based on whet ...


4
David Craddock, Thomas A Gregg, Dan F Greiner, Eric N Lais: Translation of input/output addresses to memory addresses. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, April 18, 2017: US09626298

An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to i ...


5
Dan F Greiner, Christian Jacobi, Timothy J Slegel: Constrained transaction execution. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, August 22, 2017: US09740521

Constrained transactional processing is provided. A constrained transaction is initiated by execution of a Transaction Begin constrained instruction. The constrained transaction has a number of restrictions associated therewith. Absent violation of a restriction, the constrained transaction is to co ...


6
Dan F Greiner, Christian Jacobi, Timothy J Slegel: Transactional processing. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, September 19, 2017: US09766925

A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the tran ...


7
Brenton F Belmar, Christian Jacobi, Randall W Philley, Timothy J Slegel: Facilitating transaction completion subsequent to repeated aborts of the transaction. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, August 22, 2017: US09740549

Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction ...


8
Jonathan D Bradbury, Eric M Schwarz: Vector checksum instruction. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, August 15, 2017: US09733938

A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an ...


9
Jonathan D Bradbury, Eric M Schwarz: Vector checksum instruction. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, August 22, 2017: US09740483

A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an ...


10
Jonathan D Bradbury: Vector galois field multiply sum and accumulate instruction. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, July 11, 2017: US09703557

A Vector Galois Field Multiply Sum and Accumulate instruction. Each element of a second operand of the instruction is multiplied in a Galois field with the corresponding element of the third operand to provide one or more products. The one or more products are exclusively ORed with each other and ex ...



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