1
Frank J Gorishek IV, Charles R Boswell Jr, David W Smith: Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system. Advanced Micro Devices, Lawrence J Merkel, Conley Rose & Tayon PC, October 23, 2001: US06308255 (335 worldwide citation)

A computer system includes a host processor and an emulation coprocessor. The host processor includes hardware configured to execute instructions defined by a host instruction set architecture, while the emulation coprocessor includes hardware configured to execute instructions defined by a differen ...


2
Michael K Gschwind: Forming instruction groups based on decode time instruction optimization. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, June 13, 2017: US09678756 (4 worldwide citation)

Instructions are grouped into instruction groups based on optimizations that may be performed. An instruction is obtained, and a determination is made as to whether the instruction is to be included in a current instruction group or another instruction group. This determination is made based on whet ...


3
Michael K Gschwind: Forming instruction groups based on decode time instruction optimization. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, June 13, 2017: US09678757 (4 worldwide citation)

Instructions are grouped into instruction groups based on optimizations that may be performed. An instruction is obtained, and a determination is made as to whether the instruction is to be included in a current instruction group or another instruction group. This determination is made based on whet ...


4
Michael K Gschwind, Valentina Salapura: Predictive fetching and decoding for selected instructions. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, April 11, 2017: US09619230 (1 worldwide citation)

Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instructi ...


5
Michael K Gschwind, Valentina Salapura: Predictive fetching and decoding for selected instructions. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, April 11, 2017: US09619232 (1 worldwide citation)

Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instructi ...


6
Michael K Gschwind, Valentina Salapura: Predictor data structure for use in pipelined processing. GLOBALFOUNDRIES, Heslin Rothenberg Farley & Mesiti P C, Nathan Davis, Nicholas Mesiti, January 3, 2017: US09535703 (1 worldwide citation)

A predictor data structure is used for pipelined processing by a pipelined processor. The predictor data structure includes a predicted address to be used in return from execution of a selected instruction, and a predicted operating state associated with the predicted address. Based on determining a ...


7
Dan F Greiner, Christian Jacobi, Robert R Rogers, Timothy J Slegel: Selectively controlling instruction execution in transactional processing. INTERNATIONAL BUSINESS MACHINES CORPORATION, Steven Chiu Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, May 29, 2018: US09983881

Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one ...


8
Dan F Greiner, Christian Jacobi, Robert R Rogers, Timothy J Slegel: Selectively controlling instruction execution in transactional processing. INTERNATIONAL BUSINESS MACHINES CORPORATION, Steven Chiu Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, May 29, 2018: US09983882

Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one ...


9
Dan F Greiner, Christian Jacobi, Marcel Mitran, Timothy J Slegel: Transaction abort instruction specifying a reason for abort. INTERNATIONAL BUSINESS MACHINES CORPORATION, Steven Chiu Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, May 29, 2018: US09983883

A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the ...


10
Brenton F Belmar, Christian Jacobi, Randall W Philley, Timothy J Slegel: Facilitating transaction completion subsequent to repeated aborts of the transaction. INTERNATIONAL BUSINESS MACHINES CORPORATION, William A Kinnaman Jr Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, May 29, 2018: US09983915

Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction ...