1
Richard T Simko: Nonvolatile static random access memory devices. Xicor, Fitch Even Tabin Flannery & Welsh, November 10, 1981: US04300212 (168 worldwide citation)

Nonvolatile, semiconductor random access memory cells comprising a static, RAM cell and a nonvolatile memory element which may be interconnected with the static random-access memory cell by capacitative coupling, such that the RAM cell contents may be directly copied to the nonvolatile element, and ...


2
Fernando Gonzalez: Cross coupled thin film transistors and static random access memory cell. Micron Technology, Ormiston & McKinney PLLC, September 18, 2001: US06291276 (94 worldwide citation)

A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed ...


3
Yasunobu Kosa, Howard C Kirsch, Thomas F McNelly, Frank Kelsey Baker: Semiconductor device having a static-random-access memory cell. Motorola, George R Meyer, April 14, 1998: US05739564 (77 worldwide citation)

A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electric ...


4
Olivier Thomas, Perrine Batude, Arnaud Pouydebasque, Maud Vinet: SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable. Commissariat a l Energie Atomique, Oblon Spivak McClelland Maier & Neustadt L, September 6, 2011: US08013399 (55 worldwide citation)

A static random access memory cell which, on a substrate surmounted by a stack of layers, including: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are connected to a word line and are ar ...


5
Fernando Gonzalez: Structure for cross coupled thin film transistors and static random access memory cell. Micron Technology, Ormiston Korfanta Dunbar & Holland, June 17, 1997: US05640342 (55 worldwide citation)

A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed ...


6
Yee Chia Yeo, Chenming Hu, Fu Liang Yang: CMOS SRAM cell configured using multiple-gate transistors. Taiwan Semiconductor Manufacturing, Tung & Associates, March 8, 2005: US06864519 (54 worldwide citation)

A complementary metal-oxide-semiconductor static random access memory cell that is formed by a pair of P-channel multiple-gate field-effect transistors (P-MGFETs), a pair of N-channel multiple-gate field-effect transistors (N-MGFETs), a second pair of N-MGFETs that has a drain respectively connected ...


7
Sudhir K Madan: Low voltage, low power static random access memory cell. Texas Instruments Incorporated, Jacqueline J Garner, Wade James Brady, Richard L Donaldson, July 18, 2000: US06091626 (47 worldwide citation)

A ten transistor low voltage, low power static random access memory cell (10) includes a first inverter (12) cross-coupled to a second inverter (18). A series combination of a first pass transistor (24) and a first bitline select transistor (28) is connected between an output node (13) of the first ...


8
Toshiaki Yamanaka, Yoshio Sakai, Tetsuya Hayashida, Osamu Minato, Katsuhiro Shimohigashi, Toshiaki Masuhara: Stacked static random access memory cell having capacitor. Hitachi, Antonelli Terry & Wands, February 14, 1989: US04805147 (44 worldwide citation)

A static random access memory cell in which capacitors are electrically connected to storage nodes, so that the memory cell will not suffer from soft error even when it is hit by alpha particles. The memory cell has MOS transistors, capacitors constituted by two polycrystalline silicon layers, and r ...


9
Roger A Haken: Bistable logic device using trench transistors. Texas Instruments Incorporated, Richard L Donaldson, William E Hiller, Ronald O Neerings, June 16, 1992: US05122846 (42 worldwide citation)

The described embodiments of the present invention show a structure and process for fabricating this structure in which a bi-stable logic device, such as a static random access memory cell, is formed. The advantages of the described embodiments are most particularly found when in an array. In two pa ...


10
Yasunobu Kosa, Howard C Kirsch: Methods of forming a vertical field-effect transistor and a semiconductor memory cell. Motorola, George R Meyer, November 15, 1994: US05364810 (39 worldwide citation)

The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a static random access memory cell (110) having a vertical n-channel field-effect transistor (116) and a v ...