1
Kang Wook Lee, Gu Sung Kim, Dong Hyeon Jang, Seung Duk Baek, Jae Sik Chung: Chip stack package and manufacturing method thereof. Samsung Electronics, Harness Dickey & Pierce, October 2, 2007: US07276799 (259 worldwide citation)

A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an uppe ...


2
Colin P Leach: Method and apparatus for deepwater drilling. Conoco, Richard K Thomson, March 21, 1989: US04813495 (257 worldwide citation)

A method and apparatus for drilling subsea wells in water depths exceeding 3000 feet (preferably exceeding 4000 feet). Drilling mud returns are taken at the seafloor and pumped to the surface by a centrifugal pump that is powered by a seawater driven turbine. A low-differential pressure rotating hea ...


3
Soon Bum Kim, Ung Kwang Kim, Kang Wook Lee, Se Young Jeong, Young Hee Song, Sung min Sim: Method for manufacturing wafer level chip stack package. Samsung Electronics, Harness Dickey & Pierce, December 19, 2006: US07151009 (254 worldwide citation)

Provided is a method for manufacturing WLCSP devices that includes preparing at least two wafers, each wafer having a plurality of corresponding semiconductor chips, each semiconductor chip having through electrodes formed in the peripheral surface region, forming or applying a solid adhesive region ...


4
Sang Wook Park, Soon Jin Cho: Stack package and method of fabricating the same. Hyundai Electronics, Finnegan Henderson Farabow Garrett & Dunner L, April 24, 2001: US06222259 (171 worldwide citation)

Disclosed is a stack package and a method of manufacturing the same. The stack package of the present invention comprises a ceramic capsule. A pair of protruding portions are formed at both upper sides of the ceramic capsule. A first semiconductor chip is attached on the upper face of the ceramic ca ...


5
Kwan Jai Lee, Young Jae Song, Do Soo Jeong, Tae Je Cho, Suk Hong Chang, Chang Cheol Lee, Beung Seuck Song, Jong Hee Choi: Multi-chip package. Samsung Electronics, David T Millers, Skjerven Morrill MacPherson Franklin & Friel, July 11, 2000: US06087722 (167 worldwide citation)

A multi-chip stack package does not include a die pad. The elimination of the die pad provides more room for elements in the package which. Thus, a balanced inner package structure can be achieved, and a poor molding which may expose one of the package elements can be avoided. In the package, an upp ...


6
Yoon Hwa Choi, Nam Soo Lee: Stack package. Hyundai Electronics, Ladas & Parry, June 13, 2000: US06075284 (159 worldwide citation)

Disclosed is a stack package. In the stack package, at least two semiconductor chips 40 are disposed up and down. Inner leads 31 of lead frames 30 are attached at a bonding pad-disposed face of the semiconductor chip 40. The inner leads 31 are electrically connected to the bonding pads of the semico ...


7
Do Soo Jeong, Min Cheol An, Seung Ho Ahn, Hyeon Jo Jeong, Ki Won Choi: Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements. Samsung Electronics, Jones & Volentine L, April 28, 1998: US05744827 (155 worldwide citation)

A three dimensional stack package device that can realize vertical electrical interconnection of the stacked individual package devices without a cost increase or additional complicated processing steps. The three dimensional package device includes a plurality of individual semiconductor devices, e ...


8
Dong Ho Lee: stack package made of chip scale packages. Samsung Electronics, Marger Johnson & McCollom P C, March 13, 2007: US07190061 (136 worldwide citation)

A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite ...


9
Yong Chan Kim: Bottom lead semiconductor chip stack package. LG Semicon, August 17, 1999: US05939779 (125 worldwide citation)

A bottom lead semiconductor chip stack package which includes a first body and a second body. The first body includes a pair of lead frames, each lead frame having a first lead portion and a second lead portion. A protrusion enclosed in a solder extends from the first lead portion. The first body al ...


10
Myung Geun Park, Chang Jun Park, Nam Soo Lee, Hyung Gil Baik, Yoon Hwa Choi: Chip stack package utilizing a connecting hole to improve electrical connection between leadframes. Hyundai Electronics, Ladas & Parry, November 13, 2001: US06316825 (78 worldwide citation)

The present invention relates to a stack package, as well as a method for fabricating the same, the stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a ...