1
Masayuki Watanabe, Toshio Sugano, Seiichiro Tsukui, Takashi Ono, Yoshiaki Wakashima: Semiconductor integrated circuit device and method of manufacturing the same. Hitachi, Hitachi Tobu Semiconductor, Akita Electronics, Pennie & Edmonds, January 1, 1991: US04982265 (348 worldwide citation)

In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat ...


2
Mutsunori Igarashi, Takashi Mitsuhashi, Masami Murakata, Masaaki Yamada, Fumihiro Minami, Toshihiro Akiyama, Takahiro Aoki: Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method. Kabushiki Kaisha Toshiba, Foley & Lardner, July 17, 2001: US06262487 (329 worldwide citation)

There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility., achieve facility of wiring design, and reduce production cost.


3
Akihiro Nitayama, Hiroshi Takato, Fumio Horiguchi, Fujio Masuoka: MOS-type semiconductor integrated circuit device. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt, November 2, 1993: US05258635 (187 worldwide citation)

A MOS-type semiconductor integrated circuit device is provided in which MOS transistors are formed in a vertical configuration. The MOS transistors are constituted by pillar layers formed on the substrate. The outer circumferential surfaces of the pillar layers are utilized to form the gates of the ...


4
Kouichi Kumagai: SOI IGFETs having raised integration level. NEC Corporation, Sughrue Mion Zinn Macpeak & Seas PLLC, March 14, 2000: US06037617 (185 worldwide citation)

A semiconductor integrated circuit device with the SOI structure is provided, which decreases the chip area of wiring lines interconnecting p- and n-channel IGFETs, raising their integration level. This device is comprised of a semiconductor layer formed on an insulating substrate. The semiconductor ...


5
Tadahiko Sugibayashi, Tohru Mogami: Semiconductor integrated circuit and semiconductor integrated circuit device. NEC Corporation, Katten Muchin Zavis Rosenman, February 4, 2003: US06515511 (174 worldwide citation)

A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes a wire selection portion and a logic gate portion. The logic gate portion has a MOS transistor. The wir ...


6
Kazuo Yano, Yasuhiko Sasaki: Semiconductor integrated circuit device and production method thereof. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, December 3, 1996: US05581202 (165 worldwide citation)

The semiconductor integrated circuit enjoys a high performance and can be produced at a low production cost and within a short time. A cell has an internal circuit connection such that an output terminal is connected to a plurality of input terminals through source-drain paths of active devices conn ...


7
Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake: SRAM having load transistor formed above driver transistor. Hitachi, Antonelli Terry Stout & Kraus, November 10, 1998: US05834851 (161 worldwide citation)

Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and ...


8
Naofumi Ohashi, Hizuru Yamaguchi, Junji Noguchi, Nobuo Owada: Semiconductor integrated circuit device and fabrication process thereof. Hitachi, Antonelli Terry Stout & Kraus, February 6, 2001: US06184143 (159 worldwide citation)

In a semiconductor integrated circuit wherein an interlayer insulating film is formed over a semiconductor substrate having a semiconductor device formed thereover; and an interconnection embedded in an interconnection groove in the interlayer insulating film is formed by the deposition of a metal f ...


9
Kazuhiko Kobayashi, Kou Miyazaki: Method of manufacturing semiconductor integrated circuit device. Hitachi, Antonelli Terry Stout & Kraus, July 1, 2003: US06588005 (154 worldwide citation)

A wiring pattern is divided into sets of long wiring (L1) and sets of short wiring (Ls) by comparison to a reference value. Layout rules of the sets of long wiring (L1) are made different from layout rules of the sets of short wiring (Ls) by using an effect of a Levenson type phase shift. Thereby, a ...


10
Ryuji Shibata, Shigeru Shimada: Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device. Hitachi, Antonelli Terry Stout & Kraus, October 8, 2002: US06462978 (150 worldwide citation)

In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capabl ...