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Boaz Eitan: Self-aligned split gate EPROM. Wafer Scale Integration, Alan H MacPherson, Steven F Caserza, Richard Franklin, January 27, 1987: US04639893 (64 worldwide citation)

A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. ...


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Boaz Eitan: Self-aligned split gate EPROM. WaferScale Integration, Skjerven Morrill MacPherson Franklin & Friel, September 19, 1989: US04868629 (35 worldwide citation)

A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. ...


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Boaz Eitan: Self-aligned split gate eprom process. WaferScale Integration, Alan H MacPherson, Gideon Gimlan, Forrest E Gunnison, January 3, 1989: US04795719 (29 worldwide citation)

A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. ...


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Gary Y Hong: Manufacture of the fieldless split-gate EPROM/Flash EPROM. United Microelectronics Corporation, George O Saile, Graham S Jones II, January 31, 1995: US05385856 (9 worldwide citation)

A device and method of manufacturing the device comprising a self-aligned, split-gate EPROM/Flash EPROM array device. Ions are implanted into locations in a doped well in a substrate to form buried bit lines, a forming a thick dielectric over the implanted ions, implanting a first threshold voltage ...


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Gary Y Hong: Fieldless split-gate EPROM/Flash EPROM. United Microelectronics Corporation, George O Saile, Graham S Jones II, December 26, 1995: US05479036 (5 worldwide citation)

A device and method of manufacturing the device comprising a self-aligned, split-gate EPROM/Flash EPROM array device. Ions are implanted into locations in a doped well in a substrate to form buried bit lines, a forming a thick dielectric over the implanted ions, implanting a first threshold voltage ...


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Eitan Boaz: Self-aligned split gate eprom.. Waferscale Integration, February 25, 1987: EP0211632-A2 (4 worldwide citation)

A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. ...


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Eitan Boaz: Self-aligned split gate eprom. Waferscale Integration, May 15, 1998: JP1998-125816

PROBLEM TO BE SOLVED: To make floating gates so that a misalignment between the floating gate and source region has no influence on the memory cell operation by aligning a first end of the floating gate with one end of the drain region and placing the second end of the floating gate on the channel r ...


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