1
Seung Cheol Oh: Row redundancy circuit and method for a semiconductor memory device with a double row decoder. Samsung Electronics, Charles R Donohoe, Stephen R Whitt, October 24, 1995: US05461587 (30 worldwide citation)

A row redundancy circuit for use in a semiconductor memory device having one memory cell array, and first and second main row decoders and first and second spare row decoders formed on both sides of the memory cell array includes a first fuse box for receiving addresses and, during the occurrence of ...


2
Dong Il Suh, Tae Sung Jang, Dae Je Chin: Semiconductor memory device having improved redundancy efficiency. Samsung Electronics, Stephen R Whitt, Robert A Westerlund, Charles R Donohoe, October 25, 1994: US05359560 (28 worldwide citation)

A row redundancy circuit for use in a semiconductor memory device. The row redundancy circuit providing fuse boxes to repair defective normal memory cells even in the adjacent normal memory cell arrays.


3
Hyung Kyu Lim, Jae Yeong Do, Rustam Mehta: Redundancy circuit for use in a semiconductor memory device. SamSung Semiconductor & Telecommunication, Robert E Bushnell, December 27, 1988: US04794568 (20 worldwide citation)

A normal decoder and a redundant decoder having address program devices are used for the replacement of bad cells. The number of address program devices is one more than the number of input address bits for selecting a normal row or column. The input signals of the additional program device are comp ...


4
Soo Man Hwang, Chang Ho Do: Row redundancy circuit using a fuse box independent of banks. Hyundai Electronics, Jacobson Holman PLLC, March 5, 2002: US06353570 (10 worldwide citation)

A row redundancy circuit for use in a semiconductor memory device of the present invention having a fuse box independent of banks so as to improve repair efficiency. The row redundancy circuit includes a fuse box coupled to a row address and a bank address from an address buffer in which a fuse corr ...


5
Hwang Soo Man, Do Chang Ho: Row redundancy circuit using a fuse box independent of banks. Hyundai Electronics Ind, February 27, 2002: GB2366018-A

A row redundancy circuit for use in a semiconductor memory device of the present invention uses a fuse box independent of banks so as to improve repair efficiency. For this purpose, in the semiconductor memory device, the row redundancy circuit includes a fuse box (210) coupled to a row address and ...


6
Lim Hyung Kyu, Do Jae Yeong, Mehta Rustam: Redundancy circuit for use in a semiconductor memory device. Samsung Semiconductor Tele, November 13, 1987: FR2598549-A1

In order to replace defective cells, use is made of a normal decoder 20 and a redundant decoder containing address program devices RAPDO0 - RAPD1, RAPDi - RAPDi+1. The number of address program devices is made greater by 1 than that of the number of input address bits for selecting a row or a normal ...


7
Lim Hyung Kyu, Do Jae Yeong, Mehta Rustam: Redundancy circuit for use in a semiconductor memory device. Samsung Semiconductor Tele, December 16, 1987: GB2191614-A

In order to replace defective cells, use is made of a normal decoder 20 and a redundant decoder containing address program devices RAPDO0 - RAPD1, RAPDi - RAPDi+1. The number of address program devices is made greater by 1 than that of the number of input address bits for selecting a row or a normal ...


8
Soo Man Hwang, Chang Ho Do: Row redundancy circuit using a fuse box independent of banks. Jacobeson Price Holman & Stern, Professional Liability Company, June 28, 2001: US20010005335-A1

A row redundancy circuit for use in a semiconductor memory device of the present invention having a fuse box independent of banks so as to improve repair efficiency. The row redundancy circuit includes a fuse box coupled to a row address and a bank address from an address buffer in which a fuse corr ...


9
Seung Cheol Oh: Row redundancy circuit and method for a semiconductor memory device with a double row decoder. Samsung Electronics, WANG ZHONGZHONG XIAO JUCHANG, January 17, 1996: CN94116042

A row redundancy circuit for use in a semiconductor memory device having one memory cell array, and first and second main row decoders and first and second spare row decoders formed on both sides of the memory cell array includes a first and second fuse box, during the occurrence of a defective addr ...


10