1
George J Barlow, Chester M Nibby Jr, Robert B Johnson: Pause apparatus for a memory controller with interleaved queuing apparatus. Honeywell Information Systems, Faith F Driscoll, John S Solakian, December 10, 1985: US04558429 (32 worldwide citation)

A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for ...


2
Barlow George J, Nibby Chester M Jr, Johnson Robert B: Dispositif de retardement pour controleur de memoires avec dispositif de mise en file dattente a entrelacements, Pause apparatus for a memory controller with interleaved queuing apparatus. Honeywell Information Systems, SMART & BIGGAR, February 12, 1985: CA1182578

ABSTRACT OF THE DISCLOSURE A data processing system includes a plurality ofmemory command generating units which connect to a commonbus network with a number of memory subsystems. Eachsubsystem includes a controller which controls theoperation of a number of memory module units and includesa number ...