1
Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand Jr: Parallel slice processor with dynamic instruction stream mapping. INTERNATIONAL BUSINESS MACHINES CORPORATION, Mitch Harris Atty at Law, Andrew M Harris, Steven L Bennett, May 30, 2017: US09665372 (8 worldwide citation)

A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices a ...


2
Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand Jr: Parallel slice processor with dynamic instruction stream mapping. INTERNATIONAL BUSINESS MACHINES CORPORATION, Mitch Harris Atty at Law, Andrew M Harris, Steven L Bennett, June 27, 2017: US09690585 (7 worldwide citation)

A method of operation of a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues coupled by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the ...


3
Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand Jr: Processing of multiple instruction streams in a parallel slice processor. INTERNATIONAL BUSINESS MACHINES CORPORATION, Mitch Harris Atty at Law, Andrew M Harris, Steven L Bennett, June 27, 2017: US09690586 (7 worldwide citation)

A method of managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices provides instruction processing flexibility. An event is detected indicating that either resource requirement or resource availability for a subseq ...


4
Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand Jr: Processing of multiple instruction streams in a parallel slice processor. INTERNATIONAL BUSINESS MACHINES CORPORATION, Mitch Harris Atty at Law, Andrew M Harris, Steven L Bennett, June 6, 2017: US09672043 (7 worldwide citation)

Techniques for managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices provide flexibility in execution of program instructions by a processor core. An event is detected indicating that either resource requirement o ...


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PARALLEL SLICE PROCESSOR WITH DYNAMIC INSTRUCTION STREAM MAPPING. INTERNATIONAL BUSINESS MACHINES CORPORATION, November 12, 2015: US20150324204-A1

A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices a ...


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PARALLEL SLICE PROCESSOR WITH DYNAMIC INSTRUCTION STREAM MAPPING. November 12, 2015: US20150324206-A1

A method of operation of a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues coupled by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the ...


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PROCESSING OF MULTIPLE INSTRUCTION STREAMS IN A PARALLEL SLICE PROCESSOR. June 15, 2017: US20170168837-A1

A method of managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices. An event is detected indicating that either resource requirement or resource availability for a subsequent instruction of an instruction stream wi ...