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Tetsuo Endoh, Yoshiyuki Tanaka, Seiichi Aritome, Riichiro Shirota, Susumu Shuto, Tomoharu Tanaka, Gertjan Hemink, Toru Tanzawa: Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, June 30, 1998: US05774397 (592 worldwide citation)

A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate seque ...


2
Tomoharu Tanaka, Jian Chen: Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell. Kabushiki Kaisha Toshiba, SanDisk Corporation, Banner & Witcoff, November 4, 2003: US06643188 (300 worldwide citation)

A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL t ...


3
Kito Takashi, Aochi Hideaki, Katsumata Ryuta, Nitayama Akihiro, Kito Masaru, Tanaka Hiroyasu: Non-volatile semiconductor memory device and manufacturing method therefor. Toshiba, October 11, 2007: JP2007-266143 (263 worldwide citation)

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device which has a novel structure, wherein memory cells are stacked three-dimensionally and which can reduce the chip area.SOLUTION: The non-volatile semiconductor memory device includes a plurality of memory strings, to which a p ...


4
Kenji Kohda, Tsuyoshi Toyama, Nobuaki Ando, Kenji Noguchi, Shinichi Kobayashi: Non-volatile semiconductor memory device with facility of storing tri-level data. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc and Becker, June 4, 1991: US05021999 (215 worldwide citation)

A non-volatile memory cell includes a MOS transistor of double gate construction. The MOS memory transistor includes a floating gate structure which includes electrically separated first and second segmented floating gates (4a; 4b). For the purpose of writing data, electrons are independently inject ...


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Kikuzo Sawada, Toshio Wada: Non-volatile semiconductor memory device capable of storing multi-value data in each memory cell. Nippon Steel Corporation, Pollock Vande Sande & Priddy, May 2, 1995: US05412601 (152 worldwide citation)

An electrically erasable non-volatile semiconductor memory device comprising a plurality of row lines and column lines, a plurality of memory cells connected in a matrix to the plurality of row lines and column lines, a selection circuit for selecting a desired one of the plurality of memory cells, ...


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Hsing Lan Lung, Tao Cheng Lu, Mam Tsung Wang: 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate. Sonnenschein Nath & Rosenthal, March 20, 2001: US06204529 (149 worldwide citation)

The present application discloses a non-volatile semiconductor memory device for storing up to eight-bits of information. The device has a semiconductor substrate of one conductivity type, a central bottom diffusion region on top of a portion of the semiconductor substrate, a second semiconductor la ...


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Yasuo Itoh, Koji Sakui: Non-volatile semiconductor memory device. Kabushiki Kaisha Toshiba, Banner & Witcoff, August 22, 2000: US06107658 (146 worldwide citation)

In a NAND EEPROM using the local self-boosting system, an intermediate voltage which allows a memory cell adjacent to a selected memory cell to be turned on is applied to the control gate of the adjacent memory cell. As a result, even if the adjacent memory cell is in a normally-off state, the poten ...


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Tsukasa Ooishi: Non-volatile semiconductor memory device allowing shrinking of memory cell. Renesas Technology, Buchanan Ingersoll & Rooney PC, April 24, 2007: US07208751 (139 worldwide citation)

Dummy cells are disposed in alignment with memory cells arranged in rows and columns in a memory array. The memory cell includes a variable resistance element and a select transistor having a collector connected to a substrate region and selecting the variable resistance element in response to a row ...


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Koji Hosono, Kenichi Imamiya, Hiroshi Nakamura, Mikito Nakabayashi, Koichi Kawai: Non-volatile semiconductor memory device. Kabushiki Kaisha Toshiba, Hogan & Hartson, June 14, 2005: US06907497 (135 worldwide citation)

A non-volatile semiconductor memory device includes a memory cell array, a data hold circuit, and a controller A program control function applies a program voltage to a selected memory cell to let data shift from a first logic state to a second logic state. A program verify control function verifies ...


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Tetsuo Fujii, Nobuyoshi Sakakibara, Toshio Sakakibara, Hiroshi Iwasaki: Non-volatile semiconductor memory device. Nippondenso, Cushman Darby & Cushman, September 27, 1988: US04774556 (134 worldwide citation)

A non-volatile semiconductor memory device comprises a semiconductor substrate of a first conduction type, an impurity buried layer of a second conduction type formed at the surface of the semiconductor substrate for constituting either one of a drain region or a source region, an epitaxial layer of ...