1
Ka Y Leung, Jean Luc Nauleau: Multiple die layout for facilitating the combining of an individual die into a single die. SILICON LABORATORIES, Trop Pruner & Hu P C, October 17, 2017: US09793240

An apparatus includes a wafer portion and a plurality of die fabricated in the wafer portion in a defined pattern such that the die are separated from each other by a dicing area or a street. The apparatus includes a conductive connection between given adjacent die. The conductive connection is elec ...


2
Ka Y Leung, Jean Luc Nauleau: Multiple die layout for facilitating the combining of an individual die into a single die. Silicon Laboratories, March 31, 2011: US20110073996-A1

A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically inter ...