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Takao Akaogi, Lee Edward Cleveland, Kendra Nguyen: Multiple bank simultaneous operation for a flash memory. Advanced Micro Devices, Fujitsu, Brinks Hofer Gilson & Lione, May 29, 2001: US06240040 (159 worldwide citation)

An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write ope ...


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Akaogi Takao, Kendra Nguyen, Lee Edward Cleveland: Multiple bank simultaneous operation for a flash memory. Auvanced Micro Devices, ge bo cheng wei, May 21, 2003: CN01806325 (1 worldwide citation)

An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write ope ...


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Akaogi Takao, Nguyen Kendra, Cleveland Lee Edward: Multiple bank simultaneous operation for a flash memory. Advanced Micro Devices, Fujitsu, sRODDY Richard J, September 20, 2001: WO/2001/069603

An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write ope ...


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Akaogi Takao, Nguyen Kendra, Cleveland Lee Edward: Multiple bank simultaneous operation for a flash memory. Advanced Micro Devices, Fujitsu, December 18, 2002: EP1266377-A2

An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write ope ...


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Akaogi Takao, Nguyen Kendra, Cleveland Lee Edward: Multiple bank simultaneous operation for a flash memory. Spansion, February 17, 2003: KR1020027012128

An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write ope ...


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