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Chin Hsiung Hsu, Chun Chih Yang: Methods for reducing congestion region in layout area of IC. MEDIATEK, McClure Qualey & Rodack, April 10, 2018: US09940422

A method for reducing congestion regions of an integrated circuit is provided. A placement of the IC is obtained, wherein the placement includes a signal path between a first macro module and a second macro module. The signal path passes through a routing area of the placement for transmitting a spe ...


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METHODS FOR REDUCING CONGESTION REGION IN LAYOUT AREA OF IC. July 14, 2016: US20160203254-A1

A method for reducing congestion regions of an integrated circuit is provided. A placement of the IC is obtained, wherein the placement includes a signal path between a first macro module and a second macro module. The signal path passes through a routing area of the placement for transmitting a spe ...