1
Taber H Smith, Vikas Mehrotra, David White: Methods and systems for implementing dummy fill for integrated circuits. Cadence Design Systems, Vista IP Law Group, July 13, 2010: US07757195 (7 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


2
Taber H Smith, Vikas Mehrotra, David White: Methods and systems for implementing dummy fill for integrated circuits. Praesagus, Cadence Design Systems, c o BINGHAM MCCUTCHEN, May 3, 2007: US20070101305-A1

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...



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