1
Suresh N Rajan: Methods and apparatus of stacking DRAMs. MetaRAM, Zilka Kotab PC, May 27, 2008: US07379316 (105 worldwide citation)

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


2
Suresh N Rajan: Methods and apparatus of stacking DRAMs. MetaRAM, Zilka Kotab PC, October 6, 2009: US07599205 (76 worldwide citation)

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


3
Rajan Suresh, Smith Michael, Wang David: Methods and apparatus of stacking drams. Metaram, Rajan Suresh, Smith Michael, Wang David, ZILKA Kevin J, March 8, 2007: WO/2007/028109 (71 worldwide citation)

Large capacity memory systems (FB-DIMMs) are constructed using stacked memory integrated circuits (220) or chips (310). The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


4
Suresh N Rajan, Michael J S Smith, David T Wang: Methods and apparatus of stacking DRAMs. Google, Fish & Richardson P C, December 31, 2013: US08619452 (17 worldwide citation)

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


5
Rajan Suresh, Smith Michael, Wang David: Methods and apparatus of stacking drams. Metaram, June 11, 2008: GB2444663-A

Large capacity memory systems (FB-DIMMs) are constructed using stacked memory integrated circuits (220) or chips (310). The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


6
Suresh N Rajan: Methods and apparatus of stacking DRAMs. Stattler Johansen & Adeli, March 15, 2007: US20070058410-A1

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


7
Suresh N Rajan, Michael JS Smith, David T Wang: Methods and apparatus of stacking DRAMs. John Stattler, Stattler Johansen & Adeli, March 15, 2007: US20070058471-A1

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


8
Suresh N Rajan: Methods and apparatus of stacking drams. Zilka Kotab PC Mrm1, July 17, 2008: US20080170425-A1

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


9
Suresh N Rajan: Methods and apparatus of stacking drams. Fish & Richardson PC, January 28, 2010: US20100020585-A1

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


10
Suresh N Rajan: Methods and apparatus of stacking drams. Google, October 25, 2012: US20120268982-A1

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.



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