1
Michael A Stuber, Christopher N Brindle, Dylan J Kelly, Clint L Kemerling, George P Imthurn, Robert B Welstand, Mark L Burgener, Alexander Dribinsky, Tae Youn Kim: Method and apparatus improving gate oxide reliability by controlling accumulated charge. Peregrine Semiconductor Corporation, Jaquez & Associates, Martin J Jaquez Esq, Larry D Flesner, February 15, 2011: US07890891 (55 worldwide citation)

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwis ...


2
Michael A Stuber, Christopher N Brindle, Dylan J Kelly, Clint L Kemerling, George P Imthurn, Mark L Burgener, Alexander Dribinsky, Tae Youn Kim: Method and apparatus improving gate oxide reliability by controlling accumulated charge. Peregrine Semiconductor Corporation, Jaquez Land Richman, Martin J Jaquez Esq, February 10, 2015: US08954902 (11 worldwide citation)

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwis ...


3
Stuber Michael S, Brindle Christopher N, Kelly Dylan J, Kemerling Clint L, Imthurn George P, Welstand Robert B, Burgener Mark L, Kim Tae Youn, Dribinsky Alexander: Method and apparatus improving gate oxide reliability by controlling accumulated charge. Peregrine Semiconductor Corporation, Stuber Michael S, Brindle Christopher N, Kelly Dylan J, Kemerling Clint L, Imthurn George P, Welstand Robert B, Burgener Mark L, Kim Tae Youn, Dribinsky Alexander, FLESNER Larry D, March 29, 2007: WO/2007/035610 (10 worldwide citation)

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwis ...


4
Stuber Michael S, Brindle Christopher N, Kelly Dylan J, Kemerling Clint L, Imthurn George P, Welstand Robert B, Burgener Mark L, Kim Tae Youn, Dribinsky Alexander: Method and apparatus improving gate oxide reliability by controlling accumulated charge. Peregrine Semiconductor, May 28, 2008: EP1925030-A2 (6 worldwide citation)

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwis ...


5
Michael A Stuber, Christopher N Brindle, Dylan J Kelly, Clint L Kemerling, George P Imthurn, Robert B Welstand, Mark L Burgener, Alexander Dribinsky, Tae Youn Kim: Method and apparatus improving gate oxide reliability by controlling accumulated charge. Peregrine Semiconductor Corporation, Jaquez Land Greenhaus, Martin J Jaquez Esq, March 28, 2017: US09608619 (5 worldwide citation)

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwis ...


6
Tero Tapio Ranta: Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device. Peregrine Semiconductor Corporation, Jaquez Land Greenhaus, Martin J Jaquez Esq, Alessandro Steinfl Esq, May 30, 2017: US09667227 (3 worldwide citation)

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal compris ...


7
Alexander Dribinsky, Tae Youn Kim, Dylan J Kelly, Christopher N Brindle: Circuit and method for controlling charge injection in radio frequency switches. Peregrine Semiconductor Corporation, Jaquez Land Greenhaus, Martin J Jaquez Esq, John Land Esq, February 6, 2018: US09887695 (3 worldwide citation)

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in se ...


8
William R Smith, Jaroslaw Adamski, Dan William Nobbe, Edward Nicholas Comfoltey, Jingbo Wang: Integrated tunable filter architecture. Peregrine Semiconductor Corporation, Jaquez Land Greenhaus, Martin J Jaquez Esq, John Land Esq, June 6, 2017: US09673155 (1 worldwide citation)

An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple ...


9
Eric S Shapiro, Matt Allison: Floating body contact circuit method for improving ESD performance and switching speed. pSemi Corporation, Jaquez Land Greenhaus, Martin J Jaquez Esq, John Land Esq, April 10, 2018: US09941347

Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“ ...


10
Jianhua Lu, Hojung Ju, Chun Cheng Wang: Broadband power limiter. pSemi Corporation, Jaquez Land Greenhaus, Martin J Jaquez Esq, John Land Esq, April 3, 2018: US09935678

A broadband power limiter having a distributed architecture of multiple segments of self-actuating, adjustable power limiters, where the limiter segments are separated from each other along a signal path by intermediate matching inductors. The intermediate matching inductors are chosen to form, in c ...