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Dion Rodgers, Deborah T Marr, David L Hill, Shiv Kaushik, James B Crossland, David A Koufaty: Method and apparatus for suspending execution of a thread until a specified memory access occurs. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 22, 2008: US07363474 (59 worldwide citation)

Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of ...


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Marr Deborah T, Rodgers Scott, Hill David, Kaushik Shivnandan, Crossland James, Koufaty David: A method and apparatus for suspending execution of a thread until a specified memory access occurs. Intel, October 27, 2004: GB2400947-A (1 worldwide citation)

Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of ...


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Dion Rodgers, Deborah T Marr, David L Hill, Shiv Kaushik, James B Crossland, David A Koufaty: Method and apparatus for suspending execution of a thread until a specified memory access occurs. Intel Blakely, February 7, 2008: US20080034190-A1

Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of ...


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Dion Rodgers, Deborah T Marr, David L Hill, Shiv Kaushik, James B Crossland, David A Koufaty: Method and apparatus for suspending execution of a thread until a specified memory access occurs. Jeffrey S Draeger, Blakely Sokoloff Taylor & Zafman, July 3, 2003: US20030126186-A1

Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of ...


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Marr Deborah, Rodgers Scott, Hill David, Kaushik Shivnandan, Crossland James, Koufaty David: A method and apparatus for suspending execution of a thread until a specified memory access occurs. Intel Corporation, MALLIE Michael J, July 17, 2003: WO/2003/058447

Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of ...


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Crossland James, Hill David, Kaushik Shivnandan, Koufaty David, Marr Deborah, Rodgers Scott: Method and apparatus for suspending execution of a thread until a specified memory access occurs. Intel, wang yi, October 26, 2005: CN02826590

Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of ...


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Marr Deborah, Rodgers Scott, Hill David, Kaushik Shivnandan, Crossland James, Koufaty David: A method and apparatus for suspending execution of a thread until a specified memory access occurs. Intel Corporation, August 2, 2004: KR1020047010389

Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of ...