1
Ronald S Indeck, Ron Kaplan Cytron, Mark Allen Franklin, Roger D Chamberlain: Method and apparatus for processing financial information at hardware speeds using FPGA devices. Washington University, Thompson Coburn, November 29, 2011: US08069102 (34 worldwide citation)

A method and apparatus use decision logic deployed on a reconfigurable logic device to process a stream of financial information at hardware speeds. The decision logic can be configured to perform data reduction operations on the financial information stream. Examples of such data reductions operati ...


2
Scott Parsons, David E Taylor, David Vincent Schuehler, Mark A Franklin, Roger D Chamberlain: High speed processing of financial information using FPGA devices. IP Reservoir, Thompson Coburn, February 28, 2017: US09582831 (1 worldwide citation)

A high speed system and method for processing financial instrument order data are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to monitor a financial instrument order based on a risk profile to determine whether the order is appropriate. If determined ...


3
Scott Parsons, David E Taylor, David Vincent Schuehler, Mark A Franklin, Roger D Chamberlain: High speed processing of financial information using FPGA devices. IP RESERVOIR, Thompson Coburn, Benjamin L Volk Jr, June 6, 2017: US09672565

Methods and systems for processing financial market data using a reconfigurable logic device are disclosed. Various operations such as volume weighted average price (VWAP) operations can be performed on the financial market data using firmware logic deployed on the reconfigurable logic device to acc ...


4
Ronald S Indeck, Ron Kaplan Cytron, Mark Allen Franklin, Roger D Chamberlain: Method and Apparatus for Processing Financial Information at Hardware Speeds Using FPGA Devices. Washington University, Thompson Coburn, April 5, 2007: US20070078837-A1

A method and apparatus are disclosed for using decision logic deployed on a reconfigurable logic device to process a stream of financial information at hardware speeds. The decision logic can be configured to perform data reduction operations on the financial information stream. Examples of such dat ...


5
Ronald S Indeck, Ron Kaplan Cytron, Mark Allen Franklin, Roger D Chamberlain: Method and Apparatus for Processing Financial Information at Hardware Speeds Using FPGA Devices. Washington University, May 24, 2012: US20120130922-A1

A method and apparatus use hardware logic deployed on a reconfigurable logic device to process a stream of financial information at hardware speeds. The hardware logic can be configured to perform data reduction operations on the financial information stream. Examples of such data reductions operati ...


6
Ronald S Indeck, Ron Kaplan Cytron, Mark Allen Franklin, Roger D Chamberlain: Method and Apparatus for Processing Financial Information at Hardware Speeds Using FPGA Devices. Washington University, May 10, 2012: US20120116998-A1

A method and apparatus use a reconfigurable logic device to process a stream of financial information at hardware speeds. The reconfigurable logic device can be configured to perform data processing operations on the financial information stream. Examples of such data processing operations include d ...