1
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Group, Andrews Kurth, July 5, 2005: US06914324 (73 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...


2
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Group, Andrews Kurth, J Scott Denko, October 18, 2005: US06955945 (7 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...


3
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Group, Fish & Richardson P C, August 14, 2007: US07256484 (2 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...


4
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Group, J Scott Denko, October 7, 2004: US20040197956-A1

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...


5
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Group, J Scott Denko, March 31, 2005: US20050067683-A1

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...


6
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Group, Andrews & Kurth, March 24, 2005: US20050062144-A1

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...


7
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Group, J Scott Denko, January 1, 2004: US20040000708-A1

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...


8
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Grop, J Scott Denko, Andrews Kurth, September 16, 2004: US20040178496-A1

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...