1
Yen Jen Chang, Feipei Lai, Chia Lin Yang: Low-power SRAM memory cell. The Webb Law Firm, March 18, 2008: US07345909 (94 worldwide citation)

An SRAM memory cell that has a relatively small power consumption when writing a write value of ‘0’ to the memory cell includes cross-coupled first and second inverters, at least one read access transistor for selectively coupling a respective read bit line to a common connection node of a respectiv ...


2
John E Andersen, Louis L Hsu, Stephen Kosonocky, Li Kong Wang: Refresh control circuit for low-power SRAM applications. International Business Machines Corporation, Robert M Trepp Esq, Scully Scott Murphy & Presser, August 13, 2002: US06434076 (25 worldwide citation)

A power management circuit for an SRAM system including one or more isolated memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to local supplies during an active mode of operation. The power managemen ...


3
Chia Der Chang, Yu Ching Chang, Chien Chih Chou, Yi Tung Yen: Method for forming an improved low power SRAM contact. Taiwan Semiconductor Manufacturing, Tung & Associates, June 19, 2007: US07232762 (17 worldwide citation)

A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; fo ...


4
Jason T Su, Karthik Swaminathan: Write-assist and power-down circuit for low power SRAM applications. Marvell International, September 29, 2009: US07596012 (16 worldwide citation)

Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by ...


5
Andy Chuang, Tzong Shien Wu, Sun Chieh Chien: Method of making a low power SRAM. United Microelectronics, Rabin & Champagne P C, December 28, 1999: US06008080 (15 worldwide citation)

An SRAM is formed having the six transistor cell. The pull down transistors are formed so that no arsenic is implanted into the drains of the pull down transistors so that the drains of the pull down transistors are doped only by phosphorus implantation. The sources of the pull down transistors are ...


6
Hal Kurkowski: Memory with power supply intercept in redundancy logic. Dallas Semiconductor, Worsham Forsythe Sampels & Wooldridge, August 10, 1993: US05235548 (12 worldwide citation)

A low-power SRAM with redundant rows in each of the subarrays. Conventional redundancy logic permits defective rows to be electrically replaced by redundant rows. In addition, power supply disconnect logic permits the V.sub.DD supply voltage line for the bad row to be disconnected.


7
Tam Minh Tran, George B Jamison: Low-power SRAM E-fuse repair methodology. Texas Instruments Incorporated, Alan K Stewart, W James Brady, Frederick J Telecky Jr, December 19, 2006: US07152187 (11 worldwide citation)

A low power E-fuse repair methodology substantially removes system latency during memory and/or E-fuse farm module power-down in a device that employs E-fuse farm technology. The method maintains power to the repair registers and minimal control logic in the memories, while all other circuitry can b ...


8
Tah Kang Joseph Ting, Bor Doou Rong, Shi Huei Liu: Low power SRAM redundancy repair scheme. Etron Technology, George O Saile, Stephen B Ackerman, Douglas B Schnabel, November 4, 2003: US06643166 (8 worldwide citation)

A particular SRAM cell power scheme is disclosed. It ensures that overall chip power is reduced, by eliminating power contributed by defective memory array cells. The VSS path to the 6T memory cell is controlled via NMOS transistors. A VSS Enable (VSSEN) circuit is used to decode which block has a d ...


9
Jason T Su, Karthik Swaminathan: Write-assist and power-down circuit for low power SRAM applications. Marvell International, November 13, 2012: US08310894 (7 worldwide citation)

Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by ...


10
Jason T Su, Karthik Swaminathan: Write-assist and power-down circuit for low power SRAM applications. Marvell International, November 16, 2010: US07835217 (7 worldwide citation)

Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by ...