1
Yat Tung Lam, Pantas Sutardja: Long latency interface protocol. Marvell International, October 9, 2007: US07281065 (13 worldwide citation)

A system includes a read/write channel and a hard disk controller. The hard disk controller includes a latency-independent interface that communicates with the read/write channel. A serial control data circuit transmits a serial control data signal including serial control data, wherein the serial c ...


2
Yat Tung Lam, Pantas Sutardja: Long latency interface protocol. Marvell International, February 3, 2009: US07487268 (7 worldwide citation)

A system includes a read/write channel and a hard disk controller. The hard disk controller includes a latency-independent interface that communicates with the read/write channel. A serial control data circuit transmits a serial control data signal including serial control data, wherein the serial c ...


3
Yat Tung Lam, Pantas Sutardja: Long latency interface protocol. Marvell International, February 21, 2017: US09576606

A storage controller interface includes, on a disk controller side of the storage controller interface, a first transceiver circuit configured to transfer a first block of user data to a read channel during a write operation, and a gate transmit circuit configured to, subsequent to the first block o ...


4
Yat Tung Lam, Pantas Sutardja: Long latency interface protocol. Marvell International, October 22, 2013: US08566499

A system includes a hard disk controller configured to, using only a single pin, transfer serial information from the hard disk controller. The serial information includes control data associated with control of both write operations and read operations. The serial information includes a first bit i ...


5
Yat Tung Lam, Pantas Sutardja: Long latency interface protocol. Marvell International, May 15, 2012: US08180946

An interface configured to support a signaling protocol between a first hardware component and a second hardware component. The interface comprises a first pin, a second pin, and a third pin. The first pin is configured to provide a write clock signal sourced from the first hardware component to the ...


6
Yat Tung Lam, Pantas Sutardja: Long latency interface protocol. Marvell International, September 7, 2010: US07793028

An interface supports a signaling protocol between a first hardware component and a second hardware component. The interface includes a first pin to provide a first clock signal sourced from the first hardware component to the second hardware component during a first operation, the first operation b ...