1
Chen Hua Yu, Jing Cheng Lin, Nai Wei Liu, Jui Pin Hung, Shin Puu Jeng: Interconnect structure for wafer level package. Taiwan Semiconductor Manufacturing Company, Slater and Matsil L, September 9, 2014: US08829676 (138 worldwide citation)

A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over ...


2
Chen Hua Yu, Jing Cheng Lin, Nai Wei Liu, Jui Pin Hung, Shin Puu Jeng: Interconnect structure for wafer level package. Taiwan Semiconductor Manufacturing Company, Slater & Matsil L, January 5, 2016: US09230902 (1 worldwide citation)

A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over ...


3
Chen Hua Yu, Jing Cheng Lin, Nai Wei Liu, Jui Pin Hung, Shin Puu Jeng: Interconnect structure for wafer level package. Taiwan Semiconductor Manufacturing Company, Slater Matsil, January 24, 2017: US09553000

A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over ...


4
Chen Hua Yu, Jing Cheng Lin, Nai Wei Liu, Jui Pin Hung, Shin Puu Jeng: Interconnect Structure for Wafer Level Package. Taiwan Semiconductor Manufacturing Company, January 3, 2013: US20130001776-A1

A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over ...


5
Yu Chen Hua, Lin Jing Cheng, Liu Nai Wei, Hung Jui Pin, Jeng Shin Puu: Interconnect structure for wafer level package. Taiwan Semiconductor Manufacturing Company, lu xin fang lingmei, January 2, 2013: CN201210035759

A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over ...


6
Interconnect Structure for Wafer Level Package. November 20, 2014: US20140339696-A1

A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over ...


7
Interconnect Structure for Wafer Level Package. April 28, 2016: US20160118272-A1

A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over ...