1
Scott L Jacobs, Perwaiz Nihal, Burhan Ozmat, Henri D Schnurmann: High performance integrated circuit packaging structure. International Business Machines Corporation, Steven J Meyers, Aziz M Ahsan, March 7, 1989: US04811082 (420 worldwide citation)

A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the co ...


2
Charles W Eichelberger, Robert J Wojnarowski: Multichip integrated circuit packaging configuration and method. General Electric Company, Marvin Snyder, James C Davis Jr, November 8, 1988: US04783695 (332 worldwide citation)

A multichip integrated circuit package comprises a substrate to which is affixed one or more integrated circuit chips having interconnection pads. A polymer film overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnec ...


3
Michael Anthony Gaynes, Alan James Emerick, Viswanadham Puligandla, Charles Gerard Woychik, Jerzy Maria Zalesinski: High density integrated circuit packaging with chip stacking and via interconnections. International Business Machines Corporation, Ron Kaschak, Whitham Curtis & Whitham, December 14, 1999: US06002177 (245 worldwide citation)

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which ma ...


4
Michael Anthony Gaynes, Alan James Emerick, Viswanadham Puligandla, Charles Gerard Woychik, Jerzy Maria Zalesinski: High density integrated circuit packaging with chip stacking and via interconnections. International Business Machines Corporation, Ron Kaschak, McGuirewoods, May 22, 2001: US06236115 (208 worldwide citation)

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which ma ...


5
Debendra Mallik, Kinya Ichikawa, Terry L Sterrett, Johanna Swan: Stackable integrated circuit packaging. Intel Corporation, Buckley Maschoff & Talwalkar, March 18, 2008: US07345361 (200 worldwide citation)

A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the inte ...


6
Michael Anthony Gaynes, Alan James Emerick, Viswanadham Puligandla, Charles Gerard Woychik, Jerzy Maria Zalesinski: High density integrated circuit packaging with chip stacking and via interconnections. International Business Machines Corporation, Ronald A Kaschak, McGuireWoods, February 13, 2001: US06187678 (183 worldwide citation)

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which ma ...


7
Clinton Chao: Low-cost and ultra-fine integrated circuit packaging technique. Taiwan Semiconductor Manufacturing Company, Slater & Matsil L, August 18, 2009: US07576435 (173 worldwide citation)

A semiconductor package structure and the methods for forming the same are provided. The semiconductor package structure includes an interposer; a first plurality of bonding pads on a side of the interposer; a semiconductor chip; and a second plurality of bonding pads on a side of the semiconductor ...


8
Chee Klang Yew, Siu Waf Low, Min Yu Chan: Thin stacked integrated circuit device. Texas Instruments Incorporated, Gary C Honeycutt, Fred Telecky, October 24, 2000: US06137164 (165 worldwide citation)

A thin, stacked face-to-face integrated circuit packaging structure includes a chips attached to both major surfaces of a rigid interposer, and interconnected by printed wiring traces and vias to external solder ball contacts attached to the interposer.


9
Randolph D Schueller: Chip scale ball grid array for integrated circuit packaging. Minnesota Mining and Manufacturing Company, Matthew B McNutt, February 2, 1999: US05866949 (149 worldwide citation)

A chip scale ball grid array for integrated circuit packaging having a nonpolymer layer or support structure positioned between a semiconductor die and a substrate. The nonpolymer support structure acts to increase circuit reliability by reducing thermal stress effects and/or by reducing or eliminat ...


10
Charles W Eichelberger, Robert J Wojnarowski: Multichip integrated circuit packaging method. General Electric Company, Marvin Snyder, James C Davis Jr, April 24, 1990: US04918811 (149 worldwide citation)

A multichip integrated circuit package comprises a substrate to which is affixed one or more integrated circuit chips having interconnection pads. A polymer film overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnec ...