High Density Integrated Circuit Packaging With Chip Stacking And Via Interconnections (1 - 3 of 3 results)


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Michael Anthony Gaynes, Alan James Emerick, Viswanadham Puligandla, Charles Gerard Woychik, Jerzy Maria Zalesinski: High density integrated circuit packaging with chip stacking and via interconnections. International Business Machines Corporation, Ron Kaschak, Whitham Curtis & Whitham, December 14, 1999: US06002177 (250 worldwide citation)

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which ma ...

2
Michael Anthony Gaynes, Alan James Emerick, Viswanadham Puligandla, Charles Gerard Woychik, Jerzy Maria Zalesinski: High density integrated circuit packaging with chip stacking and via interconnections. International Business Machines Corporation, Ron Kaschak, McGuirewoods, May 22, 2001: US06236115 (213 worldwide citation)

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which ma ...

3
Michael Anthony Gaynes, Alan James Emerick, Viswanadham Puligandla, Charles Gerard Woychik, Jerzy Maria Zalesinski: High density integrated circuit packaging with chip stacking and via interconnections. International Business Machines Corporation, Ronald A Kaschak, McGuireWoods, February 13, 2001: US06187678 (188 worldwide citation)

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which ma ...