31
Alexander J Yerman, Constantine A Neugebauer: Hermetic power chip packages. General Electric Company, Paul R Webb II, James C Davis Jr, February 24, 1987: US04646129 (39 worldwide citation)

Hermetic power chip packages are constructed in building block form to reduce the cost of electrical testing of power chips. The power chip packages utilized dielectric plates with metallic sheets bonded to the dielectric plates. Electric access to at least selected terminals of a power chip is gain ...


32
William Petlock Jr: Bellows-type electrical test contact. G Donald Weber Jr, December 29, 1981: US04307928 (39 worldwide citation)

The invention is a unique test contact and connector useful in automatic testing equipment (ATE). The contact connector has a bellows-type configuration which has no internal moving or sliding parts. Compliance is effected through compression of the bellows. With a helical bellows design, the contac ...


33
Alan G Wood, Trung T Doan, Warren M Farnworth, Tim J Corbett: Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor. Micron Technology, Stephen A Gratton, December 17, 1996: US05585282 (37 worldwide citation)

A process for forming die contacting substrate for establishing ohmic contact with the die is formed with raised portions on contact members. The raised portions are dimensioned so that a compression force applied to the die against the substrate results in a limited penetration of the contact membe ...


34
Salman Akram: LOC SIMM. Micron Technology, Trask Britt & Rossa, March 3, 1998: US05723907 (35 worldwide citation)

A lead-over-chip single-in-line memory module (LOC SIMM) and method of manufacturing is disclosed that provides for shortened wire bonds and ease of rework for unacceptable semiconductor dice. More specifically, the LOC SIMM of the present invention includes a plurality of slots extending through a ...


35
Paul G Carey, Jesse B Thompson, Nicolas J Colella, Kenneth A Williams: Solar cell array interconnects. Regents of the University of California, Henry P Sartorio, L E Carnahan, November 14, 1995: US05466302 (35 worldwide citation)

Electrical interconnects for solar cells or other electronic components using a silver-silicone paste or a lead-tin (Pb-Sn) no-clean fluxless solder cream, whereby the high breakage of thin (<6 mil thick) solar cells using conventional solder interconnect is eliminated. The interconnects of this inv ...


36
Jeffery L DeDino: Display card for a battery package. The Shelby Paper Box Company, Tarolli Sundheim & Covell, September 4, 1990: US04953700 (35 worldwide citation)

A battery package includes a display card and a plastic casing rotatably mounted on the display card. The display card and the plastic casing define therebetween a plurality of compartments uniformly arranged in a circular path. Each of the compartments is provided for storing a battery. The display ...


37
Keith E Barrett: Test interposer for use with ball grid array packages, assemblies and ball grid array packages including same, and methods. Micron Technology, TraskBritt, September 17, 2002: US06452807 (34 worldwide citation)

An interposer for evaluating an electrical characteristic of a ball grid array package or of a semiconductor die thereof. The interposer includes electrically conductive vias positioned correspondingly to bond pads of the semiconductor die and to the electrical contacts or terminals of a carrier sub ...


38
Michael Seigman Peppler, Johannes Cornelis Wilhelmus Bakermans: Cable harness assembly and electrical testing machine. AMP Incorporated, Russell J Egan, September 5, 1978: US04110880 (33 worldwide citation)

An assembly apparatus is disclosed for manufacturing cable harnesses having a measured length of a multi-conductor flat flexible cable terminated by at least two electrical connectors. The assembly apparatus includes a conductor testing and cable cutting station, a connector crimp termination statio ...


39
Lee D Whetsel: Process of testing integrated circuit dies on a wafer. Texas Instruments Incorporated, Lawrence J Bassuk, Richard L Donaldson, April 4, 2000: US06046600 (32 worldwide citation)

A semiconductor wafer has integrated circuit dies formed in an array of rows and columns. Selector circuits occur in the areas between the dies and are electrically connected to the individual dies for selecting between a functional mode and a bypass mode for testing. Probe areas are formed on the p ...


40
Richard W Jarvis, Iraj Emami, John L Nistler, Michael G McIntyre: Multipurpose defect test structure with switchable voltage contrast capability and method of use. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, October 2, 2001: US06297644 (31 worldwide citation)

A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. During irradiation of the conductive lines from an electron source, the grounded conductive lines will appear darker than t ...



Click the thumbnails below to visualize the patent trend.