11
David D C Chang: Electrical test apparatus and method. AT&T, Roderick B Anderson, Kenneth M Brown, March 19, 1996: US05500605 (86 worldwide citation)

The invention is a method for testing an electronic device (10) of the type having on one side thereof an array of conductive projections, such as solder balls (15), arranged in a first configuration. An array of spring-loaded probes (25) is arranged in the first configuration. An insulative templat ...


12
Erhart E Demand: Electrical testing system including plastic window test chamber and method of using same. Temptronic Corporation, Schiller & Pandiscio, January 17, 1984: US04426619 (67 worldwide citation)

An improved system for and method of testing electrical components under temperature controlled conditions includes a chamber, within which the component can be mounted, for maintaining a predetermined environmental temperature for the component. A window forming part of a wall of the chamber includ ...


13
Lawrence R Teeple Jr: Integrated circuit carrier package test probe. Trigon, Claude Hamrick, July 20, 1982: US04340860 (67 worldwide citation)

An IC carrier package test probe including a test probe head which is formed to penetrate into the IC chip cavity of the carrier package and which includes an elastic base having a thin layer of metal foil affixed to the outer face thereof, which foil is slited for greater elasticity and which is di ...


14
Choon Leong Lou, Mei Shu Hsu: Probe card for electrical testing a chip in a wide temperature range. Star Technologies, Connolly Bove Lodge & Hutz, Larry J Hume, June 14, 2005: US06906543 (65 worldwide citation)

This disclosure provides a probe card for electrical testing a chip in a wide temperature range. The probe card includes a circuit board, a cover, a circular supporter positioned on the circuit board, at least a probe needle fixed on the circular supporter by an adhesive, and a flow line positioned ...


15
Warren M Farnworth: Stereolithographic method for applying materials to electronic component substrates and resulting structures. Micron Technology, TraskBritt, February 25, 2003: US06524346 (61 worldwide citation)

A stereolithographic method of applying material to preformed electronic components with a high degree of precision, and resulting structures. A substrate used for effecting electrical testing of semiconductor dice or a carrier substrate for same may be provided with a protective structure in the fo ...


16
Larry A Virgilio: AC power outlet ground integrity and wire test circuit device. A W Sperry Instruments, Howard C Miskin, April 29, 1997: US05625285 (55 worldwide citation)

A self-contained, plug-in, hand-held device for testing the current carrying ability of the Hot wire and the Safety Ground return of standard AC outlets which have Hot, Neutral and Ground connections. The test circuit device also detects common miswires and open connections in the AC outlet being te ...


17
Donald S Rich: Circuit handler with sectioned rail. Tovex Tech, Rohm & Monsanto, November 12, 1991: US05065089 (55 worldwide citation)

A circuit handler provides a controllable environment for monitoring of an electrical device which is being subjected to a test procedure. The controllable environment may correspond to temperature extreme on the order of -55.degree. C. and +155.degree. C. The circuit handler has a support base with ...


18
Dale B Henningson, Bruce A Purkey: Microprocessor-based hand-held electrical-testing system and method. Auto Meter Products, Jenkens & Gilchrist, August 3, 2004: US06771073 (55 worldwide citation)

The present invention provides methods and systems for testing voltage drops in positive and negative legs of an electrical system and for determining maximal current capacity of the electrical system based on the measured voltage drops. This is accomplished by connecting load leads of a testing uni ...


19
Jeff Erhardt, Khoi Phan: Full flow focus exposure matrix analysis and electrical testing for new product mask evaluation. Advanced Micro Devices, Amin & Turocy, January 28, 2003: US06513151 (54 worldwide citation)

A method for new product mask evaluation is provided. Focus exposure matrices are printed at one or more layers (e.g., active gate) on full flow production wafers. The focus exposure matrices are then analyzed to produce data that facilitates detecting printed defects. The full flow production wafer ...


20
Robert Osann Jr, Shafy Eltoukhy: Methods and apparatuses for binning partially completed integrated circuits based upon test results. Lightspeed Semiconductor Corporation, Fliesler Dubb Meyer & Lovejoy, October 17, 2000: US06133582 (53 worldwide citation)

A gate array integrated circuit wafer is formed having M-N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M-N generic metal interconnection layers. The performance and electrical testing circuits are located in the ac ...



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