1
Salman Akram: Method of fabricating a multi-chip module. Micron Technology, Trask Britt, April 10, 2001: US06214641 (138 worldwide citation)

A lead-over-chip single-in-line memory module (LOC SIMM) and method of manufacturing is disclosed that provides for shortened wire bonds and ease of rework for unacceptable semiconductor dice. More specifically, the LOC SIMM of the present invention includes a plurality of slots extending through a ...


2
Michael D Hunsaker, Barry W Darr: Test fixture for positioning and testing a magnetic head. Read Rite Corporation, Nathan N Kallman, May 29, 2001: US06237215 (124 worldwide citation)

A test fixture for assembling and electrical testing of magnetic head includes a fixed baseplate, a cage, and an X-Y positioner that is adjustably mounted on the baseplate. The cage is formed of a flat, thin, elongated arm and is secured at its rear end to the X-Y positioner. The forward end of the ...


3
Alvin M Kong, James C Lau, Steven S Chan: Mass simultaneous sealing and electrical connection of electronic devices. TRW, September 5, 1995: US05448014 (122 worldwide citation)

The present invention provides a new and effective method for the sealing and electrical testing of electronic devices; and particularly for surface acoustic wave devices. In accordance with the present invention, the cost and size of making hermetically sealed packages for electronic devices and of ...


4
Richard Allan Deckert, Steven Engelking, Joey Dean Evans: Integrated testing method and apparatus for semiconductor test operations processing. Sony Corporation, Sony Electronics, Wood Herron & Evans L, October 24, 2000: US06137303 (120 worldwide citation)

A semiconductor wafer testing and inspecting apparatus and method are provided in which a plurality of tests are performed on each of a plurality of wafers from a wafer cassette and before the wafers are returned to a packaging cassette or further processing. A carousel conveyor receives each wafer ...


5
James C K Lau, Richard P Malmgren, Kenneth Lui: Testing device for integrated circuits on wafer. TRW, December 26, 1995: US05479109 (113 worldwide citation)

An electrical testing device is provided for testing integrated circuits located on a wafer. The testing device employs a multi-layer test circuit having a plurality of contacts for contacting the integrated circuits on a wafer. The layers of the test circuit are embedded in a flexible transparent d ...


6
Luen Chian Sun: Probing of device elements. Taiwan Semiconductor Manufacturing, Tung & Associates, June 7, 2005: US06902941 (100 worldwide citation)

A new and improved method for the probing of integrated circuits (ICs) and is particularly suitable for probing various elements of an IC for failure analysis or other electrical testing and/or measurement of the IC. The method includes providing a probe access trench in the IMD (intermetal dielectr ...


7
Keith E Barrett: Test interposer for use with ball grid array packages assemblies and ball grid array packages including same and methods. Micron Technology, Trask Britt, June 27, 2000: US06081429 (95 worldwide citation)

An interposer for evaluating an electrical characteristic of a ball grid array package or of a semiconductor die thereof. The interposer includes electrically conductive vias positioned correspondingly to bond pads of the semiconductor die and to the electrical contacts or terminals of a carrier sub ...


8
Jerrold L King, Leland R Nevill: Semiconductor chip package. Micron Technology, Workman Nydegger & Seeley, March 6, 2001: US06198172 (95 worldwide citation)

An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substa ...


9
Charles C Nolan, Stuart Sahr: Temperature conditioner for tests of unpackaged semiconductors. Signatone Corporation, Linval B Castle, July 4, 1989: US04845426 (92 worldwide citation)

A prober for the electrical testing of unpackaged integrated circuits on a semiconductor wafer can test these devices between subfreezing to elevated temperatures without generating atmospheric fog or frost on the wafer or associated equipment by directing an enclosed tubular curtain of dry gas, suc ...


10
Norman B Clarke, Lawrence G Cook, Robert G Doyle, Michael Renner: Molded test probe assembly. International Business Machines Corporation, Whitham & Marhoefer, August 2, 1994: US05334931 (88 worldwide citation)

A probe 100 which can be formed from a molded plastic provides an inexpensive construction for a probe which may be readily replaced in electrical testing apparatus, particularly of the automated type. A conductive contact tip 18 is preferably co-molded into a cantilevered portion 14' of a body bloc ...



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