1
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Praesagus, Bingham McCutchen, October 17, 2006: US07124386 (251 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


2
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Praesagus, Fish & Richardson P C, December 19, 2006: US07152215 (238 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


3
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Cadence Design Systems, Bingham McCutchen, July 1, 2008: US07393755 (39 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


4
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Cadence Design Systems, Bingham McCutchen, May 27, 2008: US07380220 (25 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


5
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Cadence Design Systems, Bingham McCutchen, April 8, 2008: US07356783 (25 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


6
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Cadence Design Systems, Bingham McCutchen, April 22, 2008: US07363598 (23 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


7
David White: Dummy fill for integrated circuits. Cadence Design Systems, Vista IP Law Group, August 10, 2010: US07774726 (8 worldwide citation)

Methods and systems for correcting inter-level variations are disclosed. One approach addresses thickness and/or topological variations based upon layers in an IC design that do not allow the placement of dummy fill, in which dummy fill is added to certain layers of the IC to reduce process variatio ...


8
Taber H Smith, Vikas Mehrotra, David White: Methods and systems for implementing dummy fill for integrated circuits. Cadence Design Systems, Vista IP Law Group, July 13, 2010: US07757195 (7 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


9
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Praesagus a Massachusetts Corporation, Fish & Richardson PC, February 17, 2005: US20050037522-A1

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


10
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Praesagus a Massachusetts corporation, Fish & Richardson PC, March 10, 2005: US20050051809-A1

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...



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