1
James W Adkisson, John A Bracchitta, John J Ellis Monaghan, Jerome B Lasky, Effendi Leobandung, Kirk D Peterson, Jed H Rankin: Double planar gated SOI MOSFET structure. International Business Machines Corporation, Michael E Whitham, Eugene I Shkurko, Mark F Chadurjian, November 19, 2002: US06483156 (132 worldwide citation)

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by ...


2
James W Adkisson, John A Bracchitta, John J Ellis Monaghan, Jerome B Lasky, Effendi Leobandung, Kirk D Peterson, Jed H Rankin: Double planar gated SOI MOSFET structure. International Business Machines Corporation, William D Sabo, Whitham Curtis & Christofferson P C, December 9, 2003: US06660596 (22 worldwide citation)

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by ...


3
James W Adkisson, John A Bracchitta, John J Ellis Monaghan, Jerome B Lasky, Effendi Leobandung, Kirk D Peterson, Jed H Rankin: Double planar gated SOI MOSFET structure. International Business Machines Corporation, Whitham Curtis & Christofferson PC, October 24, 2002: US20020153587-A1 (2 worldwide citation)

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by ...



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