1
Matthew Guthaus, Xuchu Hu: Distributed resonant clock grid synthesis. The Regents of the University of California, Adam Warwick Bell, Matthew Rupert Kaser, May 6, 2014: US08719748 (2 worldwide citation)

A method of implementing a VLSI clock network is implemented. That method includes a step of generating an initial VLSI clock grid for incorporation on a silicon die. An input grid buffer is then sized and implemented for the VLSI clock grid. LC tanks are then placed and sized in the VLSI clock grid ...


2
DISTRIBUTED RESONANT CLOCK GRID SYNTHESIS. The Regents of the University of California Office of Technology Transfer, June 20, 2013: US20130154727-A1

A method of implementing a VLSI clock network is implemented. That method includes a step of generating an initial VLSI clock grid for incorporation on a silicon die. An input grid buffer is then sized and implemented for the VLSI clock grid. LC tanks are then placed and sized in the VLSI clock grid ...


3
LC RESONANT CLOCK RESOURCE MINIMIZATION USING COMPENSATION CAPACITANCE. The Regents of the University of California, November 23, 2017: US20170338772-A1

VLSI distributed LC resonant clock networks having reduced inductor dimensions as well as simplified decoupling capacitances that are obtained by including one or more compensation capacitors. A compensation capacitor can be added in parallel with a clock capacitance and/or in parallel with a clock ...