1
John Bulzachelli: Clock recovery circuit without jitter peaking. Analog Devices, Wolf Greenfield & Sacks, July 30, 1991: US05036298 (19 worldwide citation)

A voltage-controlled delay is connected in series with a phase-locked loop. The voltage-controlled delay is controlled by the control voltage developed by the phase-locked loop amplifier and filter. With this arrangement, the amplifier and filter can be designed to have a transfer function that does ...


2
Bulzachelli John F: Clock recovery circuit without jitter peaking.. Analog Devices, February 10, 1993: EP0526573-A1 (1 worldwide citation)

A voltage-controlled delay is connected in series with a phase-locked loop. The voltage-controlled delay is controlled by the control voltage developed by the phase-locked loop amplifier and filter. With this arrangement, the amplifier and filter can be designed to have a transfer function that does ...


3
Bulzachelli John F: Clock recovery circuit without jitter peaking. Analog Devices, KUDIRKA Paul E, October 31, 1991: WO/1991/016766

A voltage-controlled delay (418) is connected in series with a phase-locked loop (430). The voltage-controlled delay is controlled by the control voltage developed by the phase-locked loop amplifier and filter (410). With this arrangement, the amplifier and filter can be designed to have a transfer ...