1
Peter Gillingham, Bruce Millar: High bandwidth memory interface. Mosaid Technologies Incorporated, Pillay Kevin Fasken Martineau DuMoulin, January 21, 2003: US06510503 (248 worldwide citation)

This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem compr ...


2
Robert T Durst Jr, Kevin D Hunter: Method and system for preventing unauthorized use of software. Robert H Whisker, Melvin J Scolnick, David E Pitchenik, May 12, 1992: US05113518 (216 worldwide citation)

A technique is disclosed for preventing a computer program from being used by a computer system other than a designated system. The values of certain characteristics exhibited by the designated computer system first are stored, and then the values of those same characteristics exhibited by the compu ...


3
Mitsuyoshi Yamamoto, Ikuya Kawasaki, Hideo Inayoshi, Susumu Narita, Masaharu Kubo: Data processor and single-chip microcomputer with changing clock frequency and operating voltage. Hitachi, Antonelli Terry Stout & Kraus, July 7, 1998: US05778237 (207 worldwide citation)

A microcomputer has a clock generator capable of changing the frequency of an output clock signal: and a power circuit capable of changing the level of an operating voltage to be outputted. The frequencies of clock signals and the levels of operating voltages to be individually fed to a plurality of ...


4
Ronnie M Harrison, Brent Keeth: Synchronous clock generator including a compound delay-locked loop. Micron Technology, Seed and Berry, January 4, 2000: US06011732 (185 worldwide citation)

A synchronous clock generator is comprised of a delay-locked loop for producing a plurality of signals in response to an external clock signal. Each of the plurality of signals is delayed a predetermined period of time with respect to the external clock signal. A plurality of multiplexers is respons ...


5
William L Abbott, Hung C Nguyen, Kenneth E Johnson: Disk drive using PRML class IV sampling data detection with digital adaptive equalization. Quantum Corporation, David B Harrison, August 23, 1994: US05341249 (162 worldwide citation)

A class IV partial response, maximum likelihood data channel for a disk drive includes an encoder connected to a data sequencer for converting user data blocks into a predetermined 8/9ths code such as a (0,4,4,) code. A precoder converts the 8/9ths code into class IV code. An analog write driver sup ...


6
Victor Allen Vega, John Howard Rolin: Active electrostatic transceiver and communicating system. Motorola, Terri S Hughes, August 28, 2001: US06282407 (146 worldwide citation)

An active electrostatic transceiver is provided that has electrostatic electrodes, an energy storage means such as a battery and a transceiver circuit for communication within an electrostatic RFID communication system. The transceiver circuit includes power management features so that the energy st ...


7
Bhupendra K Ahuja: Skew-free clock signal distribution network in a microprocessor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 26, 1994: US05307381 (143 worldwide citation)

A clock signal distribution network in a microprocessor for distributing a global clock signal to a plurality of units of the microprocessor includes a clock generator for generating a first clock signal with an input delay. A phase locked loop circuit generates a controllable delay to the first clo ...


8
Brent Keeth, Terry R Lee, Kevin Ryan, Troy A Manning: Method and apparatus for bit-to-bit timing correction of a high speed memory bus. Micron Technology, Dorsey & Whitney, December 9, 2003: US06662304 (135 worldwide citation)

A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a plurality of digital signals applied to respective latches in the packetized memory device. A clock gen ...


9
Henry F Lada Jr, Hung Q Le, James H Garrett, John M Gromala: Multiple frequency phase-locked loop clock generator with stable transitions between frequencies. Compaq Computer Corporation, Vinson & Elkins, August 25, 1992: US05142247 (132 worldwide citation)

A phase-locked loop (PLL) clock generator circuit which is capable of changing the frequency of its outpt clock signal in a stable fashion. Selection of the frequency of the output clock signal is made by way of a selectable frequency divider coupled between the reference clock signal and an input o ...


10
Douglas D Gephardt, James R MacDonald, Rita M O Brien: Power management architecture including a power management messaging bus for conveying an encoded activity signal for optimal flexibility. Advanced Micro Devices, B Noel Kivlin, February 20, 1996: US05493684 (130 worldwide citation)

An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controlle ...