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Taber H Smith, Vikas Mehrotra, David White: Characterization and reduction of variation for integrated circuits. Cadence Design Systems, Bingham McCutchen, June 3, 2008: US07383521 (262 worldwide citation)

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.


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Taber H Smith, Vikas Mehrotra, David White: Characterization and reduction of variation for integrated circuits. Cadence Design Systems, Vista IP Law Group, August 16, 2011: US08001516 (28 worldwide citation)

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.


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Taber H Smith, Vikas Mehrotra, David White: Characterization and reduction of variation for integrated circuits. Praesagus a Massachusetts corporation, Fish & Richardson PC, June 16, 2005: US20050132306-A1

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.


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Taber H SMITH, Vikas MEHROTRA, David WHITE: Characterization and reduction of variation for integrated circuits. Cadence Design Systems, Vista Ip Law Group, January 29, 2009: US20090031261-A1

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.


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