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Christopher Paul Miller, Jim Lewis Rogers, Steven William Tomashot: Cached synchronous DRAM architecture allowing concurrent DRAM operations. International Business Machines Corporation, Robert A Walsh, July 28, 1998: US05787457 (145 worldwide citation)

A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture includes a synchronous dynamic random access memory (SDRAM) bank including a row decoder coupled to a memory bank array for selecting a row of data in the memory bank array, sense amplifiers coup ...


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Jim L Rogers, Steven W Tomashot, Christopher P Miller: Cached synchronous dram architecture allowing concurrent dram operations. International Business Machines Corporation, August 11, 1998: TW338129

A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture including asynchronous dynamic random access memory (SDRAM) bank including a row decoder coupled to a memory bank array for selecting a row of data in the memory bank array, sense amplifiers coup ...


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