1
Jega A Arulpragasam, Robert A Giggi, Richard F Lary, Daniel T Sullivan: Cached multiprocessor system with pipeline timing. Digital Equipment Corporation, Cesari and McKenna, July 5, 1983: US04392200 (103 worldwide citation)

A multiprocessor data processing system, the processors (30) and input/output devices (32) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), a memory management circuit (22) and an address translation circuit (24). The data processing system further inclu ...


2
Jega A Arulpragasam, Robert A Giggi, Richard F Lary, Daniel T Sullivan: Relating to cached multiprocessor system with pipeline timing. Digital Equipment Corporation, Cesari & McKenna, August 17, 1982: US04345309 (35 worldwide citation)

A cached multiprocessor system operates in an ordered pipeline timing sequence in which the time slot for use of the cache is made long enough to permit only one cache access. Further, the time slot for data transfers to and from the processors succeeds the time slot for accessing the cache. The seq ...


3
Arulpragasam Jega A, Giggi Robert A, Lary Richard F, Sullivan Daniel T: Cached multiprocessor system with pipeline timing.. Digital Equipment, March 10, 1982: EP0046781-A1

A multiprocessor data processing system including a main memory system, the processors (30) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), for accessing copies of memory data therein without undue delay in retrieving data from the main memory system. A ...


4
Arulpragasam Jega A, Lary Richard F, Giggi Robert A, Sullivan Daniel T: Systeme multiprocesseur a antememoire avec syncronisation du pipeline, Cached multiprocessor system with pipeline timing. Digital Equipment Corporation, SMART & BIGGAR, August 16, 1983: CA1152222

ABSTRACT OF THE DISCLOSURE A pipelined multiprocessing system including a main corememory and a shared write-through cache memory that maintainsreadily accessible copies of data in the main core memory. A com-mon control unit (CCU) receives commands from the processors in apipelined fashion thereby ...


5
Cached multiprocessor system with pipeline timing. Digital Equipment, January 6, 1982: GB2078408-A

A multiprocessor data processing system including a main memory system, the processors (30) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), for accessing copies of memory data therein without undue delay in retrieving data from the main memory system. A ...


6
Cached multiprocessor system with pipeline timing. August 6, 1981: WO/1981/002210

A multiprocessor data processing system including a main memory system, the processors (30) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), for accessing copies of memory data therein without undue delay in retrieving data from the main memory system. A ...