71
Sau Ching Wong, Hock Chuen So, Stanley J Kopec Jr, Robert F Hartmann: Programmable logic device with array blocks with programmable clocking. Altera Corporation, Robert R Jackson, March 27, 1990: US04912342 (221 worldwide citation)

A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitab ...


72
Dzung Joseph Tran, Mark W Acuff: Exclusive or/nor circuit. Translogic Technology, Kolisch Hartwell Dickinson McCormack & Heuser, March 12, 2002: US06356112 (220 worldwide citation)

A digital circuit configured to receive three or more input signals and produce an output signal corresponding to either an XOR or XNOR of the input signals. In one embodiment of the invention, the circuit includes a first section connected in series with a second section to form a three-input XOR o ...


73
Gerald O Crowther, Terence A Douglas, Howard M Farmer: Remote control system capable of transmitting the information with the aid of an infra red beam using PPM or an ultrasonic beam using PDM. U S Philips Corporation, Thomas A Briody, William J Streeter, Edward W Goodman, October 28, 1980: US04231031 (220 worldwide citation)

A remote control system for TV receiver control. The system uses infra-red transmission to trasmit an infra-red data pulse on each edge of a pulse duration signal comprising a coded pattern of binary 0 and 1 bits which are formed by pulses of respective different lengths. The original pulse duration ...


74
David E Jefferson, Cameron McClintock, James Schleicher, Andy L Lee, Manuel Mejia, Bruce B Pedersen, Christopher F Lane, Richard G Cliff, Srinivas T Reddy: Programmable logic device architecture with super-regions having logic regions and a memory region. Altera Corporation, Robert R Jackson, Fish & Neave, April 10, 2001: US06215326 (219 worldwide citation)

A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a pl ...


75
David W Caldwell, Nicholas W Medendorp: Touch sensor panel with hidden graphic mode. Donnelly Corporation, Price Heneveld Cooper DeWitt & Litton, August 24, 1993: US05239152 (219 worldwide citation)

A capacitive touch sensor panel includes a generally planar substrate, a graphic layer behind the substrate defining user readable graphic symbols and a light source behind the graphic layer including individual selectively actuatable light elements behind particular ones of the graphic symbols. A f ...


76
Mehdi Hamidi Sani, Gregory A Uvieghara: Non-volatile multi-threshold CMOS latch with leakage control. Qualcomm Incorporated, Philip R Wadsworth, Charles D Brown, Timothy F Loomis, September 21, 2004: US06794914 (215 worldwide citation)

An integrated circuit including a Multi-Threshold CMOS (MTCMOS) latch combining low voltage threshold CMOS circuits with high voltage threshold CMOS circuits. The low voltage threshold circuits including a majority of the circuits in the signal path of the latch to ensure high performance of the lat ...


77
Larry Pileggi, Herman Schmit: Programmable gate array based on configurable metal interconnect vias. Carnegie Mellon University, Thorp Reed & Armstrong, October 14, 2003: US06633182 (215 worldwide citation)

A method is comprised of translating a bit stream defining the state of switches of an FPGA into a set of via geometries, or generating the set of via geometries directly from a physical design system. The via geometries are used to produce at least one via mask. The via mask is then used in a manuf ...


78
Richard G Cliff: Coarse-grained look-up table architecture. Altera Corporation, Townsend & Townsend & Crew, September 29, 1998: US05815726 (214 worldwide citation)

A new programmable logic device architecture with an improved LAB and improved interconnection resources. For interconnecting signals to and from the LABs (200), the global interconnection resources include switch boxes (310), long lines (340 and 350), double lines (360 and 370), single lines (385), ...


79
William C Phillips, Michael V Pascale, Ronald W Minarik, Kenneth M Schmidt, Benjamin F Weigand, Walter M Dirndorfer, Robert S Prill, Arnold B Siegel, Richard H Nogay: Common receive module for a programmable digital radio. Northrop Grumman Corporation, Walter G Sutcliff, January 12, 1999: US05859878 (213 worldwide citation)

A digital submodule is included in a software programmable common receive module for receiving IF signals and producing a serial bit stream. The digital submodule is programmable based on a selected application of a plurality of radio applications and, if present, a selected function of a plurality ...


80
Benjamin S Ting: Architecture and interconnect scheme for programmable logic circuits. BTR, Blakely Sokoloff Taylor & Zafman, October 10, 1995: US05457410 (213 worldwide citation)

An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a ...