51
Andre DeHon, Thomas F Knight Jr, Edward Tau, Michael Bolotski, Ian Eslick, Derrick Chen, Jeremy Brown: Dynamically programmable gate array with multiple contexts. Massachusetts Institute of Technology, Hamilton Brook Smith & Reynolds P C, April 21, 1998: US05742180 (259 worldwide citation)

An integrated dynamically programmable gate array comprises a two dimensional array of programmable gates. These gates can be implemented as look up tables but hardwired gates with programmable interconnections are also possible. Each one of the gates receives plural input logic signals from plural ...


52
Robert A Boie, Laurence W Ruedisueli, Eric R Wagner: Computer mouse or keyboard input device utilizing capacitive sensors. AT&T IPM, Geoffrey D Green, October 31, 1995: US05463388 (258 worldwide citation)

A computer input device for use as a computer mouse or keyboard comprises a thin, insulating surface covering an array of electrodes. Such electrodes are arranged in a grid pattern and can be connected in columns and rows. Each column and row is connected to circuitry for measuring the capacitance s ...


53
Shoichi Masui, Michiya Oura, Tsuzumi Ninomiya, Wataru Yokozeki, Kenji Mukaida: Programmable logic device with ferroelectric configuration memories. Fujitsu, Arent Fox PLLC, August 2, 2005: US06924663 (254 worldwide citation)

A programmable logic device with ferroelectric configuration memories storing multiple configuration data sets. The device has programmable logic blocks, interconnections, and I/O blocks to provide desired logic functions. Those building blocks can be dynamically reconfigured by changing the selecti ...


54
Stephen M Trimberger: PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays. Xilinx, Adam H Tachner, Jeanette S Harms, July 4, 2000: US06084429 (253 worldwide citation)

A window pane architecture for FPGAs utilizes spaced subarrays having routing channels therebetween. In one embodiment, at least one routing channel includes segmented and staggered routing wires to minimize current loading and capacitive time delay. Connections between the configurable logic blocks ...


55
Ross H Freeman, Hung Cheng Hsieh: Distributed memory architecture for a configurable logic array and method for using distributed memory. Xilinx, Edel M Young, Patrick T Bever, August 30, 1994: US05343406 (252 worldwide citation)

Additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array ...


56
Brian C Faith, Thomas Oelsner, Gary N Lai: Configurable computational unit embedded in a programmable device. QuickLogic Corporation, Skjerven Morrill, November 19, 2002: US06483343 (250 worldwide citation)

A plurality of configurable computational units are embedded in a programmable device, such as a field programmable gate array. Each configurable computational unit includes an adder circuit that is switchably coupled to a multiplier circuit and an accumulator circuit. The configurable computational ...


57
F Erich Goetting, Stephen M Trimberger: Logic cell for field programmable gate array having optional internal feedback and optional cascade. Xilinx, Edel M Young, November 15, 1994: US05365125 (247 worldwide citation)

The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The o ...


58
Alice I Biber, Douglas W Stout: Self-adjusting impedance matching driver. International Business Machines Corporation, J Dennis Moore, July 28, 1992: US05134311 (242 worldwide citation)

A self-adjusting impedance matching driver for a digital circuit. The driver has both a pull-up gate to VDD and a pull-down gate to ground. An array of gates is provided in parallel with each of the pull-up gate and the pull-down gate, with any one or more of such gates being selectively enabled in ...


59
Danesh Tavana, Wilson K Yee, Stephen M Trimberger: Integrated circuit with field programmable and application specific logic areas. Xilinx, Edel M Young, Adam H Tachner, Lois D Cartier, October 20, 1998: US05825202 (235 worldwide citation)

A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By int ...


60
William W Leong, Richard G Cliff, Cameron McClintock: Programmable logic array device with grouped logic regions and three types of conductors. Altera Corporation, Jeffrey H Ingerman, Fish & Neave, July 16, 1996: US05537057 (233 worldwide citation)

A programmable logic array device in which programmable logic regions are arranged in groups of four is provided. The device includes direct connect conductors for carrying signals totally within one group of four regions as well as to certain adjacent programmable logic regions, local conductors fo ...