1
Ross H Freeman: Configurable electrical circuit having configurable logic elements and configurable interconnects. Xilinx, Skjerven Morrill MacPherson Franklin & Friel, September 26, 1989: US04870302 (718 worldwide citation)

A configurable logic array comprises a plurality of configurable logic elements variably interconnected in response to control signals to perform a selected logic function. Each configurable logic element in the array is in itself capable of performing any one of a plurality of logic functions depen ...


2
Alice I Biber, Douglas W Stout: Self-adjusting impedance matching driver. International Business Machines Corporation, J Dennis Moore, July 28, 1992: US05134311 (242 worldwide citation)

A self-adjusting impedance matching driver for a digital circuit. The driver has both a pull-up gate to VDD and a pull-down gate to ground. An array of gates is provided in parallel with each of the pull-up gate and the pull-down gate, with any one or more of such gates being selectively enabled in ...


3
Karl M J Lofgren, Gerald W Shearer, Kenneth W Ouyang: Phase-locked loop delay line. Western Digital Corporation, Horn Jubas & Lubitz Spensley, May 1, 1990: US04922141 (155 worldwide citation)

A circuit for providing precise delays includes a phase-locked loop driven by a reference frequency source such as a crystal oscillator and including a variable delay circuit. The output of the oscillator is applied to the delay circuit and the non-delayed and delayed signals are compared in a phase ...


4
James H Hesson: High speed CMOS driver circuit. Micron Technology, Angus C Fox III, November 17, 1992: US05165046 (152 worldwide citation)

A high-speed CMOS driver circuit which compensates for the intervening transmission line effects resulting from the existence of a printed circuit board, or a ceramic or silicon substrate between the coupled CMOS devices, thus preventing significant signal degradation. Several techniques are employe ...


5
Daniel Gitlin, Sheau Suey Li, Martin L Voogel, Tiemin Zhao: Pass gate circuit with body bias control. Xilinx, Patrick T Bever, Jeanette S Harms, March 9, 1999: US05880620 (140 worldwide citation)

A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the ...


6
Philip H Bird, Desmond R Armstrong: Differential amplifier and current sensing circuit including such an amplifier. U S Philips Corporation, Thomas A Briody, Jack E Haken, Jack D Slobod, December 5, 1989: US04885477 (124 worldwide citation)

A differential amplifier includes first and second matched field-effect transistors (FETs) (21,22) having their source electrodes connected together and to a current source (2), and their drain electrodes connected respectively to an input and an output of a current mirror circuit (3). The FETs (21, ...


7
Stephen L Casper: Voltage compensating CMOS input buffer. Micron Technology, David J Paul, January 11, 1994: US05278460 (103 worldwide citation)

The CMOS voltage compensating input buffer circuit of the present invention provides a means to stabilize input level trip points and is comprised of a voltage compensating circuit having an input node and an output drive node coupled to an input buffer. The voltage compensating circuit receives its ...


8
Shuichi Ishii, Tatsuya Kimura: Integrated logic circuit with clock skew adjusters. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, June 16, 1992: US05122679 (102 worldwide citation)

In an integrated logic curcuit, a plurality of clock skew adjustors generate clocks having coincident phases in reaponse to frequency information and phase information fed from a clock source. These clock source and clock adjustors are arranged so that their individual signal delays may be substanti ...


9
Eric Chen Li Sheng, Matthew Robert Ward: Adaptive control of operating and body bias voltages. Transmeta Corporation, July 14, 2009: US07562233 (101 worldwide citation)

Adaptive control of operating and body bias voltages. In accordance with a first embodiment of the present invention, a desirable operating frequency for the microprocessor is determined. Information stored within and specific to the microprocessor is accessed. The information can comprise coefficie ...


10
Stephen L Casper: Voltage compensating CMOS input buffer. Micron Technology, David J Paul, November 1, 1994: US05361002 (93 worldwide citation)

The CMOS voltage compensating input buffer circuit of the present invention provides a means to stabilize input level trip points and is comprised of a voltage compensating circuit having an input node and an output drive node coupled to an input buffer. The voltage compensating circuit receives its ...