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Yasunori Hiiragizawa: Large scale integrated circuit having functional blocks controlled with clock signals that conduct setting operations at different times. NEC Corporation, Foley & Lardner, October 5, 1999: US05963075 (55 worldwide citation)

An LSIC includes a clock distributor circuit capable of decreasing the power consumption and suppressing the deviation of the power source potential and the transient current. The circuit includes a plurality of functional blocks including CPU. The CPU conducts a data accessing operation via address ...


2
Bernard J New, Trevor J Bauer, Steven P Young: Programmable power reduction in a clock-distribution circuit. Xilinx, Lois D Cartier, June 6, 2000: US06072348 (52 worldwide citation)

A clock distribution circuit and method for programmable ICs whereby the incoming clock frequency is optionally divided by two and distributed at the new, lower frequency. Programmable dual-edge/single-edge flip-flops are provided that optionally operate at twice the frequency of the distributed clo ...


3
Stephen E Nelson, David L Duxstad, Galen C Flunker: Method for adjusting clock skew. Cray Research, Schwegman Lundberg & Woessner, November 14, 1995: US05467040 (47 worldwide citation)

A method of adjusting clock skew for a computer system, wherein the computer system includes a clock generator for generating a clock signal, at least one logic module and a clock distribution network for carrying the clock signal from the clock generator to the logic modules, includes deskewing eac ...


4
Andreas Menkhoff, Ulrich Theus: Clock generator for generating a system clock causing minimal electromagnetic interference. Deutsche ITT, Plevy & Associates, December 16, 1997: US05699005 (26 worldwide citation)

A clock generator circuit for clock controlled electronic devices, which causes minimal electromagnetic interference in adjacent electronic equipment. The clock generator circuit includes a clock source for generating a basic clock signal having a predetermined frequency. The basic clock signal defi ...


5
Hiroshi Matsumoto: Method for arranging tree-type clock signal distributing circuit with small clock skew. NEC Corporation, Foley & Lardner, May 21, 1996: US05519351 (26 worldwide citation)

In a synchronous integrated circuit including a plurality of functional blocks, the plurality of functional blocks are divided into a plurality of segments. Each of the segments is further divided into classes whose number is dependent upon the density of the functional blocks within each of the seg ...


6
Valluri R Rao, Jeffrey K Greason, Richard H Livengood: Method and apparatus for distributing a clock on the silicon backside of an integrated circuit. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 14, 2000: US06037822 (25 worldwide citation)

A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substra ...


7
Joseph H Hassoun: Variable clock divider with selectable duty cycle. Xilinx, Edward S Bever Hoffman & Harms Mao Esq, Lois D Cartier, May 9, 2000: US06061418 (24 worldwide citation)

A variable clock divider circuit is provided. The variable clock divider circuit receives an input clock signal and generates an output clock signal having an output clock frequency that is less than the input clock frequency of the input clock signal. In one embodiment, a controller generates a ris ...


8
You Ming Chiu, Jiin Lai: Gated clock tree synthesis method for the logic design. VIA Technologies, Thomas Kayden Horstemeyer & Risley, February 1, 2000: US06020774 (23 worldwide citation)

A gated clock tree synthesis (CTS) method is provided for the purpose of synthesizing a gate array logic circuit to allow optimal topological arrangement of the gate array on the logic circuit. This in turn allows the logic circuit to operate more efficiently. The logic circuit includes at least one ...


9
Brian D McMinn, Stephen C Horne: Configuration and method for testing a delay chain within a microprocessor clock generator. Advanced Micro Devices, Conley Rose & Tayon, July 4, 1995: US05430394 (19 worldwide citation)

A test configuration is provided which allows a plurality of variable delay units within a delay chain of a microprocessor clock generator to be compared with respect to one another. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurali ...


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