1
Ulrich Klostermann
Stephen L Brown, Arunava Gupta, Ulrich Klostermann, Stuart Stephen Papworth Parkin, Wolfgang Raberg, Mahesh Samant: Magnetic tunnel junctions for MRAM devices. Infineon Technologies, International Business Machines Corporation, Slater & Matsil L, December 12, 2006: US07149105 (19 worldwide citation)

Methods of manufacturing MTJ memory cells and structures thereof. A diffusion barrier is disposed between an anti-ferromagnetic layer and a pinned layer of an MTJ memory cell to improve thermal stability of the MTJ memory cell. The diffusion barrier may comprise an amorphous material or a NiFe alloy ...


2
Eugene Fitzgerald
Eugene A Fitzgerald, Nicole Gerrish: CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs. Amberwave Systems Corporation, Testa Hurwitz & Thibeault, February 20, 2003: US20030034529-A1 (6 worldwide citation)

A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained su ...


3
Eugene Fitzgerald
Eugene A Fitzgerald: Monolithically integrated light emitting devices. Massachusetts Institute of Technology, Wolf Greenfield & Sacks PC, May 10, 2007: US20070105256-A1

Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer ...


4
Eugene Fitzgerald
Eugene A Fitzgerald: Monolithically integrated silicon and III-V electronics. Massachusetts Institute of Technology, Wolf Greenfield & Sacks PC, May 10, 2007: US20070105335-A1

Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer ...


5
Bantval Jayant Baliga: Power semiconductor devices having improved high frequency switching and breakdown characteristics. North Carolina State University, Myers Bigel Sibley & Sajovec, December 7, 1999: US05998833 (350 worldwide citation)

Integrated power semiconductor devices having improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance include GD-UMOSFET unit cells with upper trench-based gate electrodes and lower trench-based source electrodes. The use of the trench ...


6
Yong Hoon Son, Jong Wook Lee: Vertical-type non-volatile memory devices. Samsung Electronics, Mills & Onello, March 16, 2010: US07679133 (258 worldwide citation)

In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate patter ...


7
Leonard Forbes, Wendell P Noble: Structure and method for reducing threshold voltage variations due to dopant fluctuations. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, November 20, 2001: US06320222 (184 worldwide citation)

An improved method and structure are provided for MOSFETs which reduce or eliminate the effects of statistical dopant fluctuations. The device includes a dual-gated FET which can be fabricated using current CMOS processing tools and process steps. The dual-gated MOSFET that has two gates one on each ...


8
Sun il Kim, Young soo Park, Jae chul Park: Thin film transistors having multi-layer channel. Samsung Electronics, Harness Dickey & Pierce, March 27, 2012: US08143678 (174 worldwide citation)

A transistor may include: a gate insulting layer; a gate electrode formed on the gate insulating layer; a channel layer formed on the gate insulating layer; and source and drain electrodes that contact the channel layer. The channel layer may have a double-layer structure, including upper and lower ...


9
Minoru Miyazaki, Akane Murakami, Baochun Cui, Mutsuo Yamamoto: Electronic circuit. Semiconductor Energy Laboratory, Eric J Nixon Peabody Robinson, December 26, 2000: US06166414 (169 worldwide citation)

An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on t ...


10
Jhon Jhy Liaw, Jeng Jung Shen: Layout for multiple-fin SRAM cell. Taiwan Semiconductor Manufacturing Company, Haynes and Boone, March 19, 2013: US08399931 (157 worldwide citation)

The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active regi ...