1
Ulrich Klostermann
Stephen L Brown, Arunava Gupta, Ulrich Klostermann, Stuart Stephen Papworth Parkin, Wolfgang Raberg, Mahesh Samant: Magnetic tunnel junctions for MRAM devices. Infineon Technologies, International Business Machines Corporation, Slater & Matsil L, December 12, 2006: US07149105 (19 worldwide citation)

Methods of manufacturing MTJ memory cells and structures thereof. A diffusion barrier is disposed between an anti-ferromagnetic layer and a pinned layer of an MTJ memory cell to improve thermal stability of the MTJ memory cell. The diffusion barrier may comprise an amorphous material or a NiFe alloy ...


2
Bantval Jayant Baliga: Power semiconductor devices having improved high frequency switching and breakdown characteristics. North Carolina State University, Myers Bigel Sibley & Sajovec, December 7, 1999: US05998833 (350 worldwide citation)

Integrated power semiconductor devices having improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance include GD-UMOSFET unit cells with upper trench-based gate electrodes and lower trench-based source electrodes. The use of the trench ...


3
Yong Hoon Son, Jong Wook Lee: Vertical-type non-volatile memory devices. Samsung Electronics, Mills & Onello, March 16, 2010: US07679133 (258 worldwide citation)

In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate patter ...


4
Darrell Rinerson, Steven W Longcor, Edmond R Ward, Steve Kuo Ren Hsia, Wayne Kinney, Christophe J Chevallier: Cross point memory array using multiple thin films. Unity Semiconductor Corporation, Beyer Weaver & Thomas, June 22, 2004: US06753561 (236 worldwide citation)

Cross point memory array using multiple thin films. The invention is a cross point memory array that uses conductive array lines and multiple thin films as a memory plug. The thin films of the memory plug include a memory element and a non-ohmic device. The memory element switches between resistive ...


5
Howard E Rhodes, Mark Durcan: Retrograde well structure for a CMOS imager. Micron Technology, Dickstein Shapiro Morin & Oshinsky, October 30, 2001: US06310366 (194 worldwide citation)

A retrograde well structure for a CMOS imager that improves the quantum efficiency and signal-to-noise ratio of the imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the well. A sin ...


6
Howard E Rhodes: CMOS imager with a self-aligned buried contact. Micron Technology, Dickstein Shapiro Morin & Oshinsky, December 4, 2001: US06326652 (180 worldwide citation)

An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from the diffusion region into the substr ...


7
Sun il Kim, Young soo Park, Jae chul Park: Thin film transistors having multi-layer channel. Samsung Electronics, Harness Dickey & Pierce, March 27, 2012: US08143678 (174 worldwide citation)

A transistor may include: a gate insulting layer; a gate electrode formed on the gate insulating layer; a channel layer formed on the gate insulating layer; and source and drain electrodes that contact the channel layer. The channel layer may have a double-layer structure, including upper and lower ...


8
Minoru Miyazaki, Akane Murakami, Baochun Cui, Mutsuo Yamamoto: Electronic circuit. Semiconductor Energy Laboratory, Eric J Nixon Peabody Robinson, December 26, 2000: US06166414 (169 worldwide citation)

An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on t ...


9
Koon Chong So: Structure to provide effective channel-stop in termination areas for trenched power transistors. MegaMOS Corporation, Bo In Lin, March 2, 1999: US05877528 (147 worldwide citation)

The present invention discloses a trenched DMOS device supported on a substrate of a first conductivity type including a core cell area which includes at least a trenched DMOS cell having a gate disposed in a trench and a drain region disposed in the substrate, the substrate further includes a termi ...


10
Fwu Iuan Hshieh, Brian H Floyd, Mike F Chang, Danny Nim, Daniel Ng: High density trench DMOS transistor with trench bottom implant. Siliconix incorporated, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, July 27, 1999: US05929481 (144 worldwide citation)

A trenched DMOS transistor overcomes the problem of a parasitic JFET at the trench bottom (caused by deep body regions extending deeper than the trench) by providing a doped trench bottom implant region at the bottom of the trench and extending into the surrounding drift region. This trench bottom i ...