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Katherina Babich
Katherina E Babich, Michael A Guillorn, Isaac Lauer, Amlan Majumdar: Thin body silicon-on-insulator transistor with borderless self-aligned contacts. International Business Machines Corporation, Fleit Gibbons Gutman Bongini & Bianco Pl, February 18, 2010: US20100038715-A1

A method for fabricating a thin-silicon-on-insulator transistor with borderless self-aligned contacts is disclosed. A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack includes a gate oxide layer on the silicon layer and a gate electrode layer on the gate oxi ...


2
Ravi Laxman
Ravi Laxman: Deposition of silicon germanium nitrogen precursors for strain engineering. Air Liquide Electronics Us, Air Liquide, Intellectual Property, June 19, 2008: US20080145978-A1

Methods for making a semiconductor device are disclosed herein. In general, the disclosed methods utilize compounds containing silicon, nitrogen, and germanium. Furthermore, the methods and compositions described are particularly applicable for formation of layers over gate structures or electrodes, ...


3
Xavier Baie
Chidambarrao Dureseti, Dokumaci Omer H, Doris Bruce B, Mandelman Jack A, Baie Xavier: Stress inducing spacers. Ibm, li zheng liu wei, November 22, 2006: CN200610082638

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


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Eugene Fitzgerald
Eugene A Fitzgerald: Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits. AmberWave Systems Corporation, Testa Hurwitz & Thibeault, January 13, 2004: US06677192 (50 worldwide citation)

Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to ...


6
Eugene Fitzgerald
Eugene A Fitzgerald, Nicole Gerrish: CMOS inverter circuits utilizing strained silicon surface channel MOSFETS. Samuels Gauthier & Stevens, September 12, 2002: US20020125471-A1 (3 worldwide citation)

A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1xGex, layer on the Si substrate, and a strained surface layer on said relaxed Si1xGex, layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained su ...


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Eugene Fitzgerald
Zhi Yuan Cheng, Eugene A Fitzgerald, Dimitri A Antoniadis, Judy L Hoyt: Process for producing semiconductor article using graded epitaxial growth. Massachusetts Institute of Technology, Testa Hurwitz & Thibeault, January 13, 2005: US20050009288-A1

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydr ...


9
Ayanori Endo, Ryo Hayashi, Tatsuya Iwasaki: Field-effect transistor and method for manufacturing the same. Canon Kabushiki Kaisha, Fitzpatrick Cella Harper & Scinto, August 12, 2008: US07411209 (2587 worldwide citation)

A method for manufacturing a field-effect transistor includes the steps of forming a source electrode and a drain electrode each containing hydrogen or deuterium; forming an oxide semiconductor layer in which the electrical resistance is decreased if hydrogen or deuterium is added; and, causing hydr ...


10
Hosono Hideo, Hirano Masahiro, Ota Hiromichi, Kamiya Toshio, Nomura Kenji: Amorphous oxide and thin film transistor. Japan Science & Tech Agency, September 8, 2010: EP2226847-A2 (2554 worldwide citation)

The present invention relates to an amorphous oxide and a thin film transistor using the amorphous oxide. In particular, the present invention provides an amorphous oxide having an electron carrier concentration less than 10 18 /cm 3 , and a thin film transistor using such an amorphous oxide. In a t ...



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