1
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Masud Beroz, Glenn Urbish, David B Tuckerman: Structure and method of forming capped chips. Tessera, Lerner David Littenberg Krumholz & Mentlik, April 1, 2008: US07351641 (6 worldwide citation)

As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern is formed on a chip insulated from wiring of the chip, and a cap is formed including a metal. The cap is joined to the metal base pattern on the chip to form t ...


2
Shyam Venkataraman
Michael Lauter, Vijay Immanuel Raman, Yuzhuo Li, Shyam Sundar Venkataraman, Daniel Kwo Hung Shen: Chemical mechanical polishing (cmp) composition comprising inorganic particles and polymer particles. Basf Se, August 16, 2012: US20120208344-A1

A chemical mechanical polishing (CMP) composition, comprising (A) at least one type of inorganic particles which are dispersed in the liquid medium (C), (B) at least one type of polymer particles which are dispersed in the liquid medium (C), (C) a liquid medium, wherein the zeta-potential of the ino ...


3
Katherina Babich
Katherina E Babich, Bruce B Doris, David R Medeiros, Devendra K Sadana: Method for tuning epitaxial growth by interfacial doping and structure including same. International Business Machines Corporation, Scully Scott Murphy & Presser PC, April 26, 2007: US20070090487-A1

A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of ...


4
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba: Method for forming a multi-layer circuit assembly. Tessera, Lerner David Litenberg Krumholz & Mentlik, October 21, 2004: US20040209439-A1

A method of making a multi-layer circuit assembly includes providing a core structure including an inner dielectric element having first and second metal layers on opposite surfaces thereof, forming one or more through vias extending through the metal layers and the inner dielectric element and coat ...


5
EUNKEE HONG
Yong Won Cha, Kyu Tae Na, Yong Soon Choi, Eunkee Hong, Ju Seon Goo: Methods of forming trench isolation layers using high density plasma chemical vapor deposition. Samsung Electronics, Myers Bigel Sibley & Sajovec P A, February 19, 2008: US07332409 (5 worldwide citation)

A method of forming a trench isolation layer can include forming an isolation layer in a trench using High Density Plasma Chemical Vapor Deposition (HDPCVD) with a carrier gas comprising hydrogen. Other methods are disclosed.


6
EUNKEE HONG
Eunkee Hong, Kyung Mun Byun, Jong Wan Choi, Eun Kyung Baek, Young Sun Kim: Method of filling a trench and method of forming an isolating layer structure using the same. Samsung Electronics, Volentine & Whitt PLLC, December 28, 2010: US07858492 (3 worldwide citation)

A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are ...


7
EUNKEE HONG
Hong Gun Kim, Eunkee Hong, Kyu Tae Na: Methods of forming semiconductor devices having multilayer isolation structures. Samsung Electronics, Myers Bigel Sibley & Sajovec, May 19, 2009: US07534698

A semiconductor device includes a first structure having a recess having a bottom and opposing side surfaces, and a second structure conformally disposed on the bottom and side surfaces of the recess. The second structure includes a multilayer having two layers having a thickness substantially small ...


8
Eugene Fitzgerald
Eugene A Fitzgerald: Monolithically integrated silicon and III-V electronics. Massachusetts Institute of Technology, Wolf Greenfield & Sacks PC, May 10, 2007: US20070105335-A1

Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer ...


9
Matthias Bauer
Matthias Bauer: Deposition of silicon germanium on silicon-on-insulator structures and bulk substrates. Knobbe Martens Olson & Bear, March 10, 2005: US20050054175-A1

Methods are provided for producing SiGe-on-insulator structures and for forming strain-relaxed SiGe layers on silicon while minimizing defects. Amorphous SiGe layers are deposited by CVD from trisilane and GeH4. The amorphous SiGe layers are recrystallized over silicon by melt or solid phase epitaxy ...


10
Jon T Fitch, Papu Maniar, Keith E Witek, Jerry Gelatos, Reza Moazzami, Sergio A Ajuria: Method of forming a semiconductor structure having an air region. Motorola, Keith E Witek, June 28, 1994: US05324683 (406 worldwide citation)

A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many ot ...