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Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, H Daniel Schnurmann, May 20, 2008: US07374987 (17 worldwide citation)

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


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Eb Eshun
Shashank S Ekbote, Kwan Yong Lim, Ebenezer Eshun, Youn Sung Choi: Silicide formation due to improved SiGe faceting. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, July 28, 2015: US09093298 (5 worldwide citation)

An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is e ...


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Xavier Baie
Doris Bruce B, Chidambarrao Dureseti, Baie Xavier, Mandelman Jack A, Sadana Devendra K, Schepis Dominic J: (fet) Having stress channel and its manufacturing method. Internatl Business Mach Corp &Lt IBM&Gt, July 8, 2004: JP2004-193596 (2 worldwide citation)

PROBLEM TO BE SOLVED: To provide a field-effect transistor whose charge carrier mobility increases by the stress of an electric current channel 22.SOLUTION: The direction of the stress is that in which a current flows (vertical direction). For a PFET device, the stress is compressive stress, while t ...


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Eb Eshun
Shashank S Ekbote, Kwan Yong Lim, Ebenezer Eshun, Youn Sung Choi: Silicide formation due to improved SiGe faceting. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, December 1, 2015: US09202883 (1 worldwide citation)

An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is e ...


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Dr. Elke Erben
Andreas Spitzer, Elke Erben: Method of manufacturing a dielectric layer and corresponding semiconductor device. Qimonds, Eschweiler & Associates, May 12, 2009: US07531405 (1 worldwide citation)

A polycrystalline dielectric layer is formed wherein the dielectric layer comprises a first dielectric material containing an oxide or nitride and a second material contributing to less than 1% in weight to the dielectric layer, forming a non-conductive oxide or nitride having an enthalpy lower than ...


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Eb Eshun
Coolbaugh Douglas D, Eshun Ebenezer E, Rassel Robert M, Slinkman James A, Zierak Michael J: Semiconductor structure and its manufacturing method. Ibm, taofeng bei, May 7, 2008: CN200610136640

The present invention provides a method for fabricating high gain FETs which substantially reduces or eliminates unwanted variation in device characteristics caused by using a prior art shadow masking process is provided. The inventive method employs a blocking mask that at least partially extends o ...


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