1
Katherina Babich
Scott D Allen, Katherina E Babich, Steven J Holmes, Arpan P Mahorowala, Dirk Pfeiffer, Richard Stephan Wise: Techniques for patterning features in semiconductor devices. International Business Machines Corporation, Ryan Mason & Lewis, Daniel P Morris, April 18, 2006: US07030008 (8 worldwide citation)

Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithograph ...


2
Eb Eshun
Himadri Sekhar Pal, Ebenezer Eshun, Shashank S Ekbote: Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, December 29, 2015: US09224653

In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional ma ...


3
Dana Gronbeck
Michael K Gallagher, Dana A Gronbeck, Timothy G Adams, Jeffrey M Calvert: Air gap formation. Shipley Company L L C, Jonathan D Baskin, August 14, 2007: US07256127 (25 worldwide citation)

A method of forming air gaps within a solid structure is provided. In this method, a sacrificial material is covered by an overlayer. The sacrificial material is then removed through the overlayer to leave an air gap. Such air gaps are particularly useful as insulation between metal lines in an elec ...


4
EUNKEE HONG
Eunkee Hong, Kyutae Na, Juseon Goo, Hong Gun Kim: Compositions including perhydro-polysilazane used in a semiconductor manufacturing process and methods of manufacturing semiconductor devices using the same. Samsung Electronics, Myers Bigel Sibley & Sajovec, March 21, 2006: US07015144 (5 worldwide citation)

Compositions that can be used in semiconductor manufacturing processes, comprising perhydro-polysilazane having a weight average molecular weight of about 300 to about 3,000 and a polydispersity index of about 1.8 to about 3.0 are provided. Solutions comprising the compositions of the present invent ...


5
Donna R Cote, David Stanasolovich, Ronald A Warren: Process for fabricating self-aligned contact studs for semiconductor structures. International Business Machines Corporation, Richard Lau, November 24, 1992: US05166096 (295 worldwide citation)

A contact stud for semiconductor structure is fabricated by providing a semiconductor substrate having an alignment structure, which includes a sidewall, and the semiconductor structure formed thereon, forming a sidewall spacer contiguous with the semiconductor structure and the sidewall of the alig ...


6
David Horsley: Method of fabricating suspended microstructures. Hewlett Packard Company, Trueman H Denny III, October 15, 2002: US06465355 (234 worldwide citation)

A method of fabricating a non-perforate suspended platform on a bonded-substrate is disclosed. The method includes forming a dielectric layer on a support surface of a base substrate followed by patterning an interface surface of the dielectric layer to define a well feature. The well feature is etc ...


7
Jiun Ren Lai, Chien Wei Chen: Pitch reduction in semiconductor fabrication. Macronix International, Stout Uxa Buyan & Mullins, May 11, 2004: US06734107 (198 worldwide citation)

A method for forming transistor devices having a reduced pitch. The pitch of the formed devices can be reduced to, e.g., half that of conventional devices by using current photolithography conditions. Since the pitch of the devices can be reduced, the device integration can be increased, resulting i ...


8
Glenn Joseph Leedy: Membrane dielectric isolation IC fabrication. Elm Technology Corporation, Burns Doane Swecker & Mathis, December 28, 1999: US06008126 (187 worldwide citation)

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semicon ...


9
Michael Kwan, Eric Liu: Gas chemistry cycling to achieve high aspect ratio gapfill with HDP-CVD. Applied Materials, Townsend & Townsend & Crew, January 1, 2002: US06335288 (182 worldwide citation)

A method and apparatus are disclosed for depositing a dielectric film in a gap having an aspect ratio at least as large as 6:1. By cycling the gas chemistry of a high-density-plasma chemical-vapor-deposition system between deposition and etching conditions, the gap may be substantially 100% filled. ...


10
George D Papasouliotis, Robert D Tas: Method of chemical modification of structure topography. Novellus Systems, Tom Chen, MacPherson Kwok Chen & Heid, September 21, 2004: US06794290 (180 worldwide citation)

A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and hydrogen etch steps. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted bef ...