1
Ulrich Klostermann
Rainer Leuschner, Ulrich Klostermann, Richard Ferrant: MRAM device structure employing thermally-assisted write operations and thermally-unassisted self-referencing operations. Qimonda, ALTIS Semiconductor SNC, November 13, 2012: US08310866 (4 worldwide citation)

A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb ...


2
Nicolas Demange
Nicolas Demange: Error test for an address decoder of a non-volatile memory. STMicroelectronics, Hogan & Hartson, November 27, 2007: US07301837 (1 worldwide citation)

A non-volatile memory includes word lines providing access to memory cells, a word-line decoder applying an activation signal corresponding to an input address to a word line, a converter reproducing the activation signal on outputs by lowering its voltage level, and an encoding circuit that include ...


3
Sanjay Mehrotra, Eliyahou Harari, Winston Lee: Multi-state EEprom read and write circuits and techniques. Sundisk Corporation, Majestic Parsons Siebert & Hsue, December 15, 1992: US05172338 (1028 worldwide citation)

Improvements in the circuits and techniques for read, write and erase of EEprom memory enable non-volatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading ...


4
Hiroyuki Kitajima, Akira Yamamoto, Takashi Doi, Masafumi Nozawa: Buffered peripheral system and method for backing up and retrieving data to and from backup memory device. Hitachi, Pennie & Edmonds, March 9, 1993: US05193154 (639 worldwide citation)

A buffered peripheral system comprises a backup memory and a primary control unit which has a buffer memory for temporarily storing a copy of the contents of a buffer memory which stores data to be written to a peripheral device and a control device for issuing a command necessary to write the block ...


5
Tetsuo Endoh, Yoshiyuki Tanaka, Seiichi Aritome, Riichiro Shirota, Susumu Shuto, Tomoharu Tanaka, Gertjan Hemink, Toru Tanzawa: Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, June 30, 1998: US05774397 (593 worldwide citation)

A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate seque ...


6
Eliyahou Harari, Robert D Norman, Sanjay Mehrotra: Flash EEPROM system with erase sector select. Sundisk Corporation, Majestic Parsons Siebert & Hsue, May 23, 1995: US05418752 (380 worldwide citation)

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected c ...


7
Sanjay Mehrotra, Eliyahou Harari, Winston Lee: Multi-state EEprom read and write circuits and techniques. SunDisk Corporation, Majestic Parsons Siebert & Hsue, November 10, 1992: US05163021 (362 worldwide citation)

Improvements in the circuits and techniques for read, write and erase of EEprom memory enable nonvolatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading i ...


8
Eliyahou Harari, Daniel C Guterman, Sanjay Mehrotra, Stephen J Gross: Method for optimum erasing of EEPROM. SunDisk Corporation, Majestic Parsons Siebert & Hsue, December 14, 1993: US05270979 (361 worldwide citation)

Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques include a 2-phase verification process interleavi ...


9
Tomoharu Tanaka, Jian Chen: Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell. Kabushiki Kaisha Toshiba, SanDisk Corporation, Banner & Witcoff, November 4, 2003: US06643188 (302 worldwide citation)

A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL t ...


10
Pierre Fazan, Serguei Okhonin: Data storage device and refreshing method for use with such device. Innovative Silicon, Neil A Steinberg, January 30, 2007: US07170807 (299 worldwide citation)

A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply ...