1
Naftali Sommer, Ofir Shalvi, Dotan Sokolov: Reading memory cells using multiple thresholds. Anobit Technologies, Fish & Richardson P C, July 5, 2011: US07975192 (103 worldwide citation)

A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performin ...


2
Griffin Jon H: Memory system having self-adjusting strobe timing. The United States of America represented by the Secretary of the Navy, January 4, 1972: US3633174 (60 worldwide citation)

An adaptive memory system comprising a core memory, utilizing externally generated read strobe pulses; an exerciser which writes a test pattern into the memory, and compares the result with a predetermined desired performance of the memory; a strobe generator which controls the exerciser and the mem ...


3
James Arthur Fisher, Anthony Andrew Lambert: Method for testing media in a library without inserting media into the library database. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Dale M Crockatt, Jennifer M Anda, May 15, 2007: US07219273 (45 worldwide citation)

A storage subsystem, method of testing storage media in the storage subsystem and program product therefor. The storage media, e.g., magnetic tape in a physical volume, is inserted into an input area in the storage subsystem, but not loaded into the subsystem library. The media input area on the phy ...


4
Benante Joseph F, Donofrio Nicholas M, Linton Richard H: Method and apparatus for determining the electrical characteristics of a memory cell having field effect transistors. International Business Machines Corporation, Galanthay Theodore E, March 5, 1974: US3795859 (32 worldwide citation)

The electrical characteristics of a field effect transistor (FET) of a memory cell connected to a ZERO bit line and of an FET of the memory cell connected to a ONE bit line are determined through applying a substantially constant voltage to one of the ZERO and ONE bit lines while changing the voltag ...


5
Yunxiang Wu, Zhengang Chen, YingQuan Wu, Ning Chen: Method of optimizing solid state drive soft retry voltages. Seagate Technology, Suiter Swantz pc llo, May 5, 2015: US09025393 (26 worldwide citation)

A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference ...


6
Thomas J Griffin, Dustin J Vanstee: Bit error rate based wear leveling for solid state drive memory. International Business Machines Corporation, Cantor Colburn, Margaret McNamara, September 9, 2014: US08832506 (20 worldwide citation)

According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER valu ...


7
Hashimoto Masashi, Hall James N: Memory access time measurement circuit and method. Texas Instruments, September 30, 1998: EP0867887-A2 (18 worldwide citation)

A circuit for measuring the access time of a memory circuit. The circuit includes a storage element 908 having an input terminal, an output terminal, and a clock terminal. The input terminal of the storage element is coupled to an output of the memory circuit 900. A clock signal source 906 is couple ...


8
Perner Frederick A, Eldredge Kenneth J, Tran Lung: Self-testing of magneto-resistive memory arrays. Hewlett Packard Co, September 12, 2001: EP1132924-A2 (17 worldwide citation)

A collection of testing circuits (106, 108, 110, 112) are disclosed which can be used to form a comprehensive built-in test system for MRAM arrays (102). The combination of testing circuits can detect MRAM array defects including: open rows (209), shorted memory cells (211), memory cells which are o ...


9
Ohtsuka Nobuaki, Miyamoto Junichi, Atsumi Shigeru: Nonvolatile semiconductor memory having a stress test circuit.. Tokyo Shibaura Electric Co, May 3, 1989: EP0314180-A2 (16 worldwide citation)

In a nonvolatile semiconductor memory, a plurality of nonvolatile semiconductor memory cells (M11 - Mmn) are arranged in a matrix form. Each of the memory cells (M11 - Mmn) is connected to corresponding one of bit lines (BL1 - BLm) and corresponding one of word lines (WL1 - WLn). The one ends of the ...


10
Ebersman Benjamin, Meehan John V, Wilson William T: Recirculating testing methods and apparatus. International Business Machines Corporation, Galanthay Theodore E, April 16, 1974: US3805152 (15 worldwide citation)

Recirculating testing methods and apparatus are employed to perform functional tests on sequential circuits arranged in an array as information storage apparatus. By measuring the propagation times through the apparatus, the AC parameters of the array are determined and the high speed performance of ...