1
Fujio Masuoka: Semiconductor memory device. Tokyo Shibaura Denki Kabushiki Kaisha, Finnegan Henderson Farabow Garrett & Dunner, August 14, 1984: US04466081 (234 worldwide citation)

A semiconductor memory device is constituted by a MOS transistor having a floating gate for storing data. An erase gate, a portion of which is under a part of the floating gate, is arranged on the MOS transistor to discharge electrons from the floating gate. The MOS transistors are arranged in a mat ...


2
Bing Yeh: Single transistor non-valatile electrically alterable semiconductor memory device. Silicon Storage Technology, Limbach Limbach & Sutton, July 2, 1991: US05029130 (229 worldwide citation)

A single transistor electrically programmable and erasable memory cell is disclosed. The single transistor has a source, a drain with a channel region therebetween, defined on a substrate. A first insulating layer is over the source, channel and drain regions. A floating gate is positioned on top of ...


3
Sameer S Haddad, Chi Chang, Antonio Matalvo, Michael A Van Buskirk: Flash EEPROM array with negative gate voltage erase operation. Advanced Micro Devices, Skjerven Morrill MacPherson Franklin & Friel, December 31, 1991: US05077691 (218 worldwide citation)

A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed ...


4
Dov Frohman Bentchkowsky, Jerry Mar, George Perlegos, William S Johnson: Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 13, 1980: US04203158 (217 worldwide citation)

An electrically programmable and electrically erasable MOS memory device suitable for high density integrated circuit memories is disclosed. Carriers are tunneled between a floating conductive gate and a doped region in the substrate to program and erase the device. A minimum area of thin oxide (70 ...


5
Kang D Suh, Jin K Kim, Jeong H Choi: Nonvolatile semiconductor memory. Samsung Electronics, Robert A Westerlund, Stephen R Whitt, Charles R Donohoe, December 5, 1995: US05473563 (193 worldwide citation)

A nonvolatile semiconductor memory device comprising an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. A selected memory b ...


6
Hunter L Scales III, William C Moyer, William D Wilson: Bus master having burst transfer mode. Motorola, Jeffrey Van Myers, January 17, 1989: US04799199 (190 worldwide citation)

A data processing system having a bus master and a memory which is capable of transferring operands in bursts of m in response to a burst request signal provided by the bus master, the operands being clustered modulo m about a selected access address provided by the bus master, where m is two (2) to ...


7
Kanji Otsuka, Kazumichi Mitsusada, Masao Sekibata, Shinji Ohnishi: Semiconductor device including an alpha-particle shield. Hitachi, Antonelli Terry & Wands, September 10, 1985: US04541003 (181 worldwide citation)

The present invention relates to a semiconductor device having a semiconductor element which is sealed by a ceramic package, wherein a shielding member is provided near it from upper surface of the semiconductor element to shield the alpha-particles radiated from the package.


8
Bruce B Roesner: Electrically programmable read-only memory stacked above a semiconductor substrate. Burroughs Corporation, Charles J Fassbender, Kevin R Peterson, April 10, 1984: US04442507 (179 worldwide citation)

In the disclosed memory, address decode means are integrated into a surface of a substrate, for addressing cells in the memory; an insulating layer covers the address decode means and the substrate; an array of spaced-apart memory cell select lines lie on the insulating layer; and outputs from the a ...


9
Albert T Wu, Ping K Ko, Tung Yi Chan, Chenming Hu: Electrically programmable memory device employing source side injection. The Regents of the University of California, Townsend and Townsend, December 27, 1988: US04794565 (177 worldwide citation)

An electrically programmable and eraseable memory element using source-side hot-electron injection. A semi-conductor substrate of a first conductivity type is provided with a source region and a drain region of opposite conductivity type and a channel region of the first conductivity type extending ...


10
Richard T Simko: Nonvolatile static random access memory devices. Xicor, Fitch Even Tabin Flannery & Welsh, November 10, 1981: US04300212 (173 worldwide citation)

Nonvolatile, semiconductor random access memory cells comprising a static, RAM cell and a nonvolatile memory element which may be interconnected with the static random-access memory cell by capacitative coupling, such that the RAM cell contents may be directly copied to the nonvolatile element, and ...